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/linux/arch/arm/boot/dts/microchip/
H A Dat91-cosino_mega2560.dts7 * HCE Engineering
18 model = "HCE Cosino Mega 2560";
19 compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9";
H A Dat91-cosino.dtsi6 * HCE Engineering
16 model = "HCE Cosino core module";
17 compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9";
/linux/drivers/ufs/host/
H A Dufshcd-pci.c102 u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); in ufs_intel_hce_enable_notify() local
104 hce |= CRYPTO_GENERAL_ENABLE; in ufs_intel_hce_enable_notify()
105 ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE); in ufs_intel_hce_enable_notify()
H A Dufs-sprd.c227 /* Key access only can be enabled under HCE enable */ in ufs_sprd_n6_key_acc_enable()
/linux/include/ufs/
H A Dufshci.h228 /* HCE - Host Controller Enable 34h */
H A Dufshcd.h306 * @hce_enable_notify: called before and after HCE enable bit is set to allow
590 * enabled via HCE register.
/linux/Documentation/arch/arm64/
H A Dbooting.rst224 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
/linux/drivers/ufs/core/
H A Dufshcd.c4939 * To initialize a UFS host controller HCE bit must be set to 1. in ufshcd_hba_execute_hce()
4940 * During initialization the HCE bit value changes from 1->0->1. in ufshcd_hba_execute_hce()
4942 * it sets the value of HCE bit to 1. The same HCE bit is read back in ufshcd_hba_execute_hce()
4944 * So without this delay the value HCE = 1, set in the previous in ufshcd_hba_execute_hce()