Searched full:hce (Results 1 – 7 of 7) sorted by relevance
| /linux/arch/arm/boot/dts/microchip/ |
| H A D | at91-cosino_mega2560.dts | 7 * HCE Engineering
18 model = "HCE Cosino Mega 2560";
19 compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9";
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| H A D | at91-cosino.dtsi | 6 * HCE Engineering
16 model = "HCE Cosino core module";
17 compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9";
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| /linux/drivers/ufs/host/ |
| H A D | ufshcd-pci.c | 102 u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); in ufs_intel_hce_enable_notify() local
104 hce |= CRYPTO_GENERAL_ENABLE; in ufs_intel_hce_enable_notify()
105 ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE); in ufs_intel_hce_enable_notify()
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| /linux/Documentation/arch/arm64/ |
| H A D | booting.rst | 224 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
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| /linux/drivers/ufs/core/ |
| H A D | ufs-mcq.c | 337 * controller disabled (HCE = 0). Reading host controller registers, e.g. the
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| H A D | ufshcd.c | 5171 * To initialize a UFS host controller HCE bit must be set to 1. in ufshcd_hba_execute_hce()
5172 * During initialization the HCE bit value changes from 1->0->1. in ufshcd_hba_execute_hce()
5174 * it sets the value of HCE bit to 1. The same HCE bit is read back in ufshcd_hba_execute_hce()
5176 * So without this delay the value HCE = 1, set in the previous in ufshcd_hba_execute_hce()
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| /linux/Documentation/devicetree/bindings/ |
| H A D | vendor-prefixes.yaml | 725 "^hce,.*":
726 description: HCE Engineering SRL
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