Searched +full:hb +full:- +full:sregs +full:- +full:l2 +full:- +full:ecc (Results 1 – 3 of 3) sorted by relevance
| /linux/Documentation/devicetree/bindings/arm/calxeda/ |
| H A D | l2ecc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
11 This does not cover the actual L2 cache controller control registers,
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-sregs-l2-ecc
26 - description: single bit error interrupt
27 - description: double bit error interrupt
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| /linux/arch/arm/boot/dts/calxeda/ |
| H A D | highbank.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
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| /linux/drivers/edac/ |
| H A D | highbank_l2_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
28 struct hb_l2_drvdata *drvdata = dci->pvt_info; in highbank_l2_err_handler()
30 if (irq == drvdata->sb_irq) { in highbank_l2_err_handler()
31 writel(1, drvdata->base + SR_CLR_SB_ECC_INTR); in highbank_l2_err_handler()
32 edac_device_handle_ce(dci, 0, 0, dci->ctl_name); in highbank_l2_err_handler()
34 if (irq == drvdata->db_irq) { in highbank_l2_err_handler()
35 writel(1, drvdata->base + SR_CLR_DB_ECC_INTR); in highbank_l2_err_handler()
36 edac_device_handle_ue(dci, 0, 0, dci->ctl_name); in highbank_l2_err_handler()
43 { .compatible = "calxeda,hb-sregs-l2-ecc", },
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