| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-sprd-adi.txt | 3 ADI is the abbreviation of Anolog-Digital interface, which is used to access
5 framework for its hardware implementation is alike to SPI bus and its timing
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
11 we can configure them to allow other hardware components to use it independently,
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
14 triggered by hardware components instead of ADI software channels.
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
17 channels, the first value specifies the hardware channel id which is used to
[all …]
|
| H A D | sprd,spi-adi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
17 framework for its hardware implementation is alike to SPI bus and its timing
21 48 hardware channels to access analog chip. For 2 software read/write channels,
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/qcom/ |
| H A D | rpmh-rsc.txt | 2 ------------
7 val) pair and triggered. Messages in the TCS are then sent in sequence over an
10 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
16 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
17 have powered off to facilitate idle power saving. TCS could be classified as -
19 ACTIVE /* Triggered by Linux */
20 SLEEP /* Triggered by F/W */
21 WAKE /* Triggered by F/W */
22 CONTROL /* Triggered by F/W */
24 The order in which they are described in the DT, should match the hardware
[all …]
|
| H A D | qcom,rpmh-rsc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in
19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | samsung-pinctrl.txt | 3 Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
[all …]
|
| H A D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
6 the pin to different hardware blocks.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/thermal/ |
| H A D | nvidia,tegra124-soctherm.txt | 4 or interrupt-based thermal monitoring, CPU and GPU throttling based
10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
13 - reg : Should contain at least 2 entries for each entry in reg-names:
14 - SOCTHERM register set
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.
16 - CCROC register set: Required for Tegra132.
17 - reg-names : Should contain at least 2 entries:
18 - soctherm-reg
[all …]
|
| H A D | nvidia,tegra124-soctherm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
[all …]
|
| /freebsd/share/man/man9/ |
| H A D | intr_event.9 | 81 Each interrupt event in the system corresponds to a single hardware or software
99 handling such as acknowledging or masking a hardware interrupt,
126 Thus, threaded handler functions may obtain non-sleepable locks, as described
280 can be used to specify additional properties of both hardware and software
315 to allow for actions such as masking and unmasking hardware interrupt signals.
317 When an interrupt is triggered, all filters are run to determine if any
329 Typically this callback masks level-triggered interrupts in an interrupt
330 controller while leaving edge-triggered interrupts alone.
335 Typically this callback unmasks level-triggered interrupts in an interrupt
345 functions return zero on success and non-zero on failure.
[all …]
|
| H A D | BUS_CONFIG_INTR.9 | 53 necessary actions are taken to actually program the hardware.
68 .Bl -tag -width ".Dv INTR_TRIGGER_CONFORM"
73 The interrupt is edge triggered.
78 The interrupt is level triggered.
87 .Bl -tag -width ".Dv INTR_POLARITY_CONFORM"
|
| /freebsd/sys/contrib/device-tree/Bindings/power/supply/ |
| H A D | mediatek,mt6370-charger.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/mediatek,mt6370-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiaEn Wu <chiaen_wu@richtek.com>
18 const: mediatek,mt6370-charger
25 After the hardware of MT6370 completes the BC1.2 detection,
26 IRQ "MT6370_IRQ_ATTACH" will be triggered, and the driver will know
28 When the IRQ "MT6370_IRQ_CHG_MIVR" is triggered, it means that the
29 hardware enters the "Minimum Input Voltage Regulation loop" and
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/interconnect/ |
| H A D | qcom,bcm-voter.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,bcm-voter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm BCM-Voter Interconnect
10 - Georgi Djakov <georgi.djakov@linaro.org>
13 The Bus Clock Manager (BCM) is a dedicated hardware accelerator that manages
22 - qcom,bcm-voter
24 qcom,tcs-wait:
26 Optional mask of which TCSs (Triggered Command Sets) wait for completion
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | ti,sci-intr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
19 triggered or level triggered interrupts and that is fixed in hardware.
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
[all …]
|
| H A D | ti,sci-intr.txt | 6 to be driven per N output. An Interrupt Router can either handle edge triggered
7 or level triggered interrupts and that is fixed in hardware.
10 +----------------------+
12 +-------+ | +------+ +-----+ |
13 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
14 +-------+ | +------+ +-----+ | controller
15 | . . | +-------+
16 +-------+ | . . |----->| IRQ |
17 | INTA |----------->| . . | +-------+
18 +-------+ | . +-----+ |
[all …]
|
| H A D | nxp,lpc3220-mic.txt | 4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
18 hardware interrupts for SIC1 and SIC2
[all …]
|
| H A D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
|
| H A D | hisilicon,mbigen-v2.txt | 6 MBI is kind of msi interrupt only used on Non-PCI devices.
12 Non-pci devices can connect to mbigen and generate the
18 -------------------------------------------
19 - compatible: Should be "hisilicon,mbigen-v2"
21 - reg: Specifies the base physical address and size of the Mbigen
25 ------------------------------------------
26 - interrupt controller: Identifies the node as an interrupt controller
28 - msi-parent: Specifies the MSI controller this mbigen use.
29 For more detail information,please refer to the generic msi-parent binding in
30 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
[all …]
|
| H A D | sifive,plic-1.0.0.txt | 1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
9 A hart context is a privilege mode in a hardware execution thread. For example,
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
13 Each interrupt can be enabled on per-context basis. Any context can claim
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
[all …]
|
| H A D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
17 A hart context is a privilege mode in a hardware execution thread. For example,
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/leds/ |
| H A D | common.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
25 led-sources:
30 $ref: /schemas/types.yaml#/definitions/uint32-array
35 from the header include/dt-bindings/leds/common.h. If there is no
42 the header include/dt-bindings/leds/common.h. If there is no matching
48 function-enumerator:
[all …]
|
| /freebsd/sys/compat/linux/ |
| H A D | linux_siginfo.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1994-1996 Søren Schmidt
42 #define LINUX_SI_QUEUE -1 /* sent by sigqueue */
43 #define LINUX_SI_TIMER -2 /* sent by timer expiration */
44 #define LINUX_SI_MESGQ -3 /* sent by real time mesq state change */
45 #define LINUX_SI_ASYNCIO -4 /* sent by AIO completion */
46 #define LINUX_SI_SIGIO -5 /* sent by queued SIGIO */
47 #define LINUX_SI_TKILL -6 /* sent by tkill system call */
62 #define LINUX___ILL_BNDMOD 11 /* (ia64) bundle-update (modification)
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | hpet.4 | 35 .Bd -ragged -offset indent
41 .Bl -ohang
47 Default value is 0xffff0000, except some known broken hardware.
57 .Bd -literal
63 controls how much per-CPU event timers should driver attempt to register.
65 IRQ, so it depends on hardware capabilities and interrupts configuration.
69 This driver uses High Precision Event Timer hardware (part of the chipset,
72 This hardware includes single main counter with known increment frequency
77 Depending on hardware capabilities and configuration, interrupt can be
81 Interrupt can be either edge- or level-triggered.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
22 to package balls is under the control of a separate pin controller hardware
38 state. See the hardware documentation for rationale. Any particular
53 controller, are both extremely non-linear. The header file
54 <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/icelake/ |
| H A D | memory.json | 33 "PublicDescription": "Counts the number of times HLE abort was triggered.",
60 …"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions a…
66 …"PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly in…
289 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not su…
303 …"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied …
317 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was…
363 …hat this does not capture all elapsed cycles while requests are outstanding - only cycles from whe…
375 "PublicDescription": "Counts the number of times RTM abort was triggered.",
413 … "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
419 …"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly in…
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/arm/keystone/ |
| H A D | ti,sci.txt | 1 Texas Instruments System Control Interface (TI-SCI) Message Protocol
2 --------------------------------------------------------------------
5 of processors have separate hardware entity which is now responsible for the
9 An example of such an SoC is K2G, which contains the system control hardware
10 block called Power Management Micro Controller (PMMC). This hardware block is
16 TI-SCI controller Device Node:
19 The TI-SCI node describes the Texas Instrument's System Controller entity node.
23 relationship between the TI-SCI parent node to the child node.
26 -------------------
27 - compatible: should be "ti,k2g-sci" for TI 66AK2G SoC
[all …]
|