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Searched +full:h8300 +full:- +full:bsc (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drenesas,h8300-bsc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,h8300-bsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Yoshinori Sato <ysato@users.sourceforge.jp>
16 - enum:
17 - renesas,h8300h-bsc
18 - renesas,h8s-bsc
19 - const: renesas,h8300-bsc
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H A Drenesas,h8300-bsc.txt4 - compatible: Must be "renesas,h8300-bsc".
5 - reg: Base address and length of BSC registers.
8 bsc: memory-controller@fee01e {
9 compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
/freebsd/sys/contrib/device-tree/src/h8300/
H A Dh8300h_sim.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #address-cells = <1>;
6 #size-cells = <1>;
7 interrupt-parent = <&h8intc>;
10 bootargs = "earlyprintk=h8300-sim";
11 stdout-path = <&sci0>;
19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <20000000>;
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H A Dh8s_sim.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #address-cells = <1>;
6 #size-cells = <1>;
7 interrupt-parent = <&h8intc>;
10 bootargs = "earlyprintk=h8300-sim";
11 stdout-path = <&sci0>;
19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <33333333>;
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H A Dedosk2674.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #address-cells = <1>;
6 #size-cells = <1>;
7 interrupt-parent = <&h8intc>;
11 stdout-path = &sci2;
20 #clock-cells = <0>;
21 compatible = "fixed-clock";
22 clock-frequency = <33333333>;
23 clock-output-names = "xtal";
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