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Searched full:gpll (Results 1 – 9 of 9) sorted by relevance

/freebsd/sys/dev/clk/rockchip/
H A Drk3399_cru.c62 GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3),
73 GATE(0, "clk_core_b_gpll_src", "gpll", 1, 3),
81 GATE(0, "gpll_cs", "gpll", 2, 9),
84 GATE(0, "gpll_cci_trace", "gpll", 2, 6),
89 GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1),
98 GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3),
129 GATE(0, "gpll_aclk_perihp_src", "gpll", 5, 0),
135 GATE(0, "gpll_aclk_emmc_src", "gpll", 6, 12),
139 GATE(0, "gpll_aclk_gmac_src", "gpll", 6, 8),
155 GATE(0, "gpll_fclk_cm0s_src", "gpll", 7, 5),
[all …]
H A Drk3568_cru.c167 PLIST(mux_armclk_p) = { "apll", "gpll" };
193 PLIST(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };
194 PLIST(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
195 PLIST(npll_gpll_p) = { "npll", "gpll" };
196 PLIST(cpll_gpll_p) = { "cpll", "gpll" };
197 PLIST(gpll_cpll_p) = { "gpll", "cpll" };
198 PLIST(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };
199 PLIST(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
206 PLIST(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
238 PLIST(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
[all …]
H A Drk3288_cru.c91 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10),
92 GATE(0, "gpll_ddr", "gpll", 0, 9),
98 GATE(0, "gpll_core", "gpll", 0, 2),
532 PLIST(cpll_gpll_p) = {"cpll", "gpll"};
533 PLIST(npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};
534 PLIST(cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};
535 PLIST(cpll_gpll_usb480m_p)= {"cpll", "gpll", "usbphy480m_src"};
536 PLIST(cpll_gpll_usb480m_npll_p) = {"cpll", "gpll", "usbphy480m_src", "npll"};
538 PLIST(mmc_p) = {"cpll", "gpll", "xin24m", "xin24m"};
552 PLIST(tspout_p) = {"cpll", "gpll", "npll", "xin27m"};
[all …]
H A Drk3328_cru.c255 GATE(0, "core_gpll_clk", "gpll", 0, 2),
315 GATE(0, "periph_gclk_src", "gpll", 4, 0),
642 PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};
643 PLIST(pll_src_cpll_gpll_apll_p) = {"cpll", "gpll", "apll"};
644 PLIST(pll_src_cpll_gpll_xin24m_p) = {"cpll", "gpll", "xin24m", "xin24m" /* Dummy */};
645 PLIST(pll_src_cpll_gpll_usb480m_p) = {"cpll", "gpll", "usb480m"};
646 PLIST(pll_src_cpll_gpll_hdmiphy_p) = {"cpll", "gpll", "hdmi_phy"};
647 PLIST(pll_src_cpll_gpll_hdmiphy_usb480m_p) = {"cpll", "gpll", "hdmi_phy", "usb480m"};
648 PLIST(pll_src_apll_gpll_dpll_npll_p) = {"apll", "gpll", "dpll", "npll"};
649 PLIST(pll_src_cpll_gpll_xin24m_usb480m_p) = {"cpll", "gpll", "xin24m", "usb480m"};
[all …]
H A Drk3568_pmucru.c77 PLIST(sclk_uart0_div_p) = { "ppll", "usb480m", "cpll", "gpll" };
88 PLIST(clk_pdpmu_p) = { "ppll", "gpll" };
96 LINK("gpll"),
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Drockchip,px30-cru.yaml55 - const: gpll
115 clock-names = "xin24m", "gpll";
H A Drockchip,px30-cru.txt17 - "gpll" for CRU (sourced from PMUCRU)
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-gru-chromebook.dtsi249 * off GPLL=600MHz, whereas some other RK3399 boards may not.
H A Dpx30.dtsi833 clock-names = "xin24m", "gpll";