| /freebsd/sys/contrib/device-tree/Bindings/power/reset/ |
| H A D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpi
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| H A D | gpio-restart.txt | 1 Drive a GPIO line that can be used to restart the system from a restart
4 This binding supports level and edge triggered reset. At driver load
5 time, the driver will request the given gpio line and install a restart
6 handler. If the optional properties 'open-source' is not found, the GPIO line
11 priority order. The gpio is configured as an output, and driven active,
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
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| /freebsd/sys/contrib/device-tree/Bindings/arm/bcm/ |
| H A D | raspberrypi,bcm2835-firmware.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/bcm/raspberrypi,bcm2835-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eric Anholt <eric@anholt.net>
11 - Stefan Wahren <wahrenst@gmx.net>
17 const: raspberrypi,bcm2835-firmware
20 - compatible
25 - const: raspberrypi,bcm2835-firmware
26 - const: simple-mfd
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | nvidia,tegra20-ac97.txt | 4 - compatible : "nvidia,tegra20-ac97"
5 - reg : Should contain AC97 controller registers location and length
6 - interrupts : Should contain AC97 interrupt
7 - resets : Must contain an entry for each entry in reset-names.
8 See ../reset/reset.txt for details.
9 - reset-names : Must include the following entries:
10 - ac97
11 - dmas : Must contain an entry for each entry in clock-names.
13 - dma-names : Must include the following entries:
14 - rx
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| H A D | rt5677.txt | 7 - compatible : "realtek,rt5677".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
13 - gpio-controller : Indicates this device is a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
20 - realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
21 - realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low.
23 - realtek,in1-differential
24 - realtek,in2-differential
25 - realtek,lout1-differential
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| H A D | cs4271.txt | 7 - compatible: "cirrus,cs4271"
10 Documentation/devicetree/bindings/spi/spi-bus.txt
14 - reg: the i2c address
19 - reset-gpio: a GPIO spec to define which pin is connected to the chip's
20 !RESET pin
21 - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
23 - cirrus,enable-soft-reset:
24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
25 line is de-asserted. That also means that clocks cannot be changed
26 without putting the chip back into hardware reset, which also requires
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| H A D | realtek,rt5677.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
30 - $ref: dai-common.yaml#
42 gpio-controller: true
44 '#gpio-cells':
47 realtek,pow-ldo2-gpio:
51 realtek,reset-gpio:
53 description: CODEC's RESET pin. Active low.
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| H A D | nvidia,tegra20-ac97.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-ac97.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-ac97
23 reset-names:
35 dma-names:
37 - const: rx
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | altera-a10sr.txt | 4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
19 a10sr_gpio GPIO Controller
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| H A D | delta,tn48m-cpld.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/delta,tn48m-cpld.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
19 It is also being used as a GPIO expander and reset controller
20 for the switch MAC-s and other peripherals.
24 const: delta,tn48m-cpld
31 "#address-cells":
34 "#size-cells":
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-385-clearfog-gtr.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
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| /freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
| H A D | hi3798cv200.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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| /freebsd/sys/dev/ath/ath_hal/ar5312/ |
| H A D | ar5312reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
33 * PCI-MAC Configuration registers (AR2315+)
35 #define AR5315_RSTIMER_BASE 0xb1000000 /* Address for reset/timer registers */
36 #define AR5315_GPIO_BASE 0xb1000000 /* Address for GPIO registers */
39 #define AR5315_RESET 0x0004 /* Offset of reset control register */
40 #define AR5315_SREV 0x0014 /* Offset of reset control register */
47 #define AR5315_GPIODIR 0x0098 /* GPIO direction register */
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| /freebsd/sys/contrib/device-tree/src/mips/ralink/ |
| H A D | mt7628a.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
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| /freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
| H A D | armada-8040-clearfog-gt-8k.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | ste-hrefv60plus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
6 #include "ste-href.dtsi"
9 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
10 compatible = "st-ericsson,hrefv60+", "st-ericsso
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-consumer-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-consumer-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common GPIO lines
10 - Bartosz Golaszewski <brgl@bgdev.pl>
11 - Linus Walleij <linus.walleij@linaro.org>
14 Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs
20 enable-gpios:
23 GPIO connected to the enable control pin.
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| H A D | gpio-xra1403.txt | 1 GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
3 The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
4 - Individually programmable inputs:
5 - Internal pull-up resistors
6 - Polarity inversion
7 - Individual interrupt enable
8 - Rising edge and/or Falling edge interrupt
9 - Input filter
10 - Individually programmable outputs
11 - Output Level Control
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| /freebsd/sys/contrib/device-tree/src/arm64/microchip/ |
| H A D | sparx5.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
28 #size-cells = <0>;
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | mmc-pwrseq-emmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple eMMC hardware reset provider
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 The purpose of this driver is to perform standard eMMC hw reset
19 doesn't have hardware reset logic connected to emmc card and (limited or
25 const: mmc-pwrseq-emmc
27 reset-gpios:
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| /freebsd/sys/contrib/device-tree/Bindings/net/ieee802154/ |
| H A D | cc2520.txt | 4 - compatible: should be "ti,cc2520"
5 - spi-max-frequency: maximal bus speed (8000000), should be set to 4000000 depends
7 - reg: the chipselect index
8 - pinctrl-0: pin control group to be used for this controller.
9 - pinctrl-names: must contain a "default" entry.
10 - fifo-gpio: GPIO spec for the FIFO pin
11 - fifop-gpio: GPIO spec for the FIFOP pin
12 - sfd-gpio: GPIO spec for the SFD pin
13 - cca-gpio: GPIO spec for the CCA pin
14 - vreg-gpio: GPIO spec for the VREG pin
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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| /freebsd/sys/contrib/device-tree/src/arm/aspeed/ |
| H A D | aspeed-bmc-facebook-harma.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/i2c/i2c.h>
11 compatible = "facebook,harma-bmc", "aspeed,ast2600";
32 stdout-path = &uart5;
40 iio-hwmon {
41 compatible = "iio-hwmon";
42 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/ |
| H A D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | usb-nop-xceiv.txt | 4 - compatible: should be usb-nop-xceiv
5 - #phy-cells: Must be 0
8 - clocks: phandle to the PHY clock. Use as per Documentation/devicetree
9 /bindings/clock/clock-bindings.txt
10 This property is required if clock-frequency is specified.
12 - clock-names: Should be "main_clk"
14 - clock-frequency: the clock frequency (in Hz) that the PHY clock must
17 - vcc-supply: phandle to the regulator that provides power to the PHY.
19 - reset-gpios: Should specify the GPIO for reset.
21 - vbus-detect-gpio: should specify the GPIO detecting a VBus insertion
[all …]
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