/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-am65-iot2050-arduino-connector.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) Siemens AG, 2018-2023 13 pinctrl-names = 15 "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown", 16 "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown", 17 "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown", 18 "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown", 19 "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown", 20 "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown", 21 "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown", [all …]
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/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 gpa0: gpa0-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 23 gpa1: gpa1-gpio-bank { [all …]
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H A D | exynos5420-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 gpy7: gpy7-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 23 gpx0: gpx0-gpio-bank { [all …]
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H A D | exynos4x12-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source 8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 pin- ## _pin { \ 16 samsung,pins = #_pin; \ 17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ 18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ 22 gpa0: gpa0-gpio-bank { 23 gpio-controller; [all …]
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H A D | exynos5410-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Exynos5410 SoC pin-mux and pin-config device tree source 9 #include "exynos-pinctrl.h" 12 gpa0: gpa0-gpio-bank { 13 gpio-controller; 14 #gpio-cells = <2>; 16 interrupt-controller; 17 #interrupt-cells = <2>; 20 gpa1: gpa1-gpio-bank { 21 gpio-controller; [all …]
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H A D | exynos4210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source 5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2011-2012 Linaro Ltd. 10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device 14 #include "exynos-pinctrl.h" 17 gpa0: gpa0-gpio-bank { 18 gpio-controller; 19 #gpio-cells = <2>; 21 interrupt-controller; [all …]
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H A D | exynos5260-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 gpa0: gpa0-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 23 gpa1: gpa1-gpio-bank { [all …]
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H A D | s5pv210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's S5PV210 SoC device tree source - pin control-related 6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. 11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are 15 #include "s5pv210-pinctrl.h" 18 pin- ## _pin { \ 19 samsung,pins = #_pin; \ 20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \ 21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \ 25 gpa0: gpa0-gpio-bank { [all …]
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H A D | exynos3250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source 8 * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 pin- ## _pin { \ 16 samsung,pins = #_pin; \ 17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \ 18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ 19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ 23 pin- ## _pin { \ [all …]
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H A D | s3c64xx-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 * - pin control-related definitions 8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are 12 #include "s3c64xx-pinctrl.h" 19 gpa: gpa-gpio-bank { 20 gpio-controller; 21 #gpio-cells = <2>; 22 interrupt-controller; 23 #interrupt-cells = <2>; 26 gpb: gpb-gpio-bank { [all …]
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/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos5433-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 pin- ## _pin { \ 16 samsung,pins = #_pin; \ 17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \ 18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ 19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \ 32 gpa0: gpa0-gpio-bank { [all …]
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H A D | exynos7-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as 12 #include "exynos-pinctrl.h" 15 gpa0: gpa0-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 interrupt-parent = <&gic>; 21 #interrupt-cells = <2>; [all …]
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H A D | exynosautov920-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source 7 * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include "exynos-pinctrl.h" 16 gpa0: gpa0-gpio-bank { 17 gpio-controller; 18 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; [all …]
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H A D | exynos850-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include "exynos-pinctrl.h" 16 gpa0: gpa0-gpio-bank { 17 gpio-controller; 18 #gpio-cells = <2>; 20 interrupt-controller; 21 #interrupt-cells = <2>; [all …]
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H A D | exynos7885-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include "exynos-pinctrl.h" 16 etc0: etc0-gpio-bank { 17 gpio-controller; 18 #gpio-cells = <2>; 20 interrupt-controller; 21 #interrupt-cells = <2>; [all …]
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H A D | exynosautov9-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source 7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as 11 #include "exynos-pinctrl.h" 14 gpa0: gpa0-gpio-bank { 15 gpio-controller; 16 #gpio-cells = <2>; 17 interrupt-controller; 18 #interrupt-cells = <2>; 19 interrupt-parent = <&gic>; [all …]
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/linux/arch/arm64/boot/dts/exynos/google/ |
H A D | gs101-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * GS101 SoC pin-mux and pin-config device tree source 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 9 #include "gs101-pinctrl.h" 12 gpa0: gpa0-gpio-bank { 13 gpio-controller; 14 #gpio-cells = <2>; 15 interrupt-controller; 16 #interrupt-cells = <2>; [all …]
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/linux/arch/arm64/boot/dts/tesla/ |
H A D | fsd-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Tesla Full Self-Driving SoC device tree source 5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2017-2021 Tesla, Inc. 11 #include "fsd-pinctrl.h" 14 gpf0: gpf0-gpio-bank { 15 gpio-controller; 16 #gpio-cells = <2>; 18 interrupt-controller; 19 #interrupt-cells = <2>; [all …]
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/linux/Documentation/devicetree/bindings/mfd/ |
H A D | brcm,bcm6362-gpio-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Broadcom BCM6362 GPIO System Controller 10 - Álvaro Fernández Rojas <noltari@gmail.com> 11 - Jonas Gorski <jonas.gorski@gmail.com> 14 Broadcom BCM6362 SoC GPIO system controller which provides a register map 15 for controlling the GPIO and pins of the SoC. 18 "#address-cells": true [all …]
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H A D | brcm,bcm6368-gpio-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Broadcom BCM6368 GPIO System Controller 10 - Álvaro Fernández Rojas <noltari@gmail.com> 11 - Jonas Gorski <jonas.gorski@gmail.com> 14 Broadcom BCM6368 SoC GPIO system controller which provides a register map 15 for controlling the GPIO and pins of the SoC. 18 "#address-cells": true [all …]
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H A D | brcm,bcm63268-gpio-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Broadcom BCM63268 GPIO System Controller 10 - Álvaro Fernández Rojas <noltari@gmail.com> 11 - Jonas Gorski <jonas.gorski@gmail.com> 14 Broadcom BCM63268 SoC GPIO system controller which provides a register map 15 for controlling the GPIO and pins of the SoC. 18 "#address-cells": true [all …]
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H A D | brcm,bcm6318-gpio-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Broadcom BCM6318 GPIO System Controller 10 - Álvaro Fernández Rojas <noltari@gmail.com> 11 - Jonas Gorski <jonas.gorski@gmail.com> 14 Broadcom BCM6318 SoC GPIO system controller which provides a register map 15 for controlling the GPIO and pins of the SoC. 18 "#address-cells": true [all …]
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H A D | brcm,bcm6328-gpio-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Broadcom BCM6328 GPIO System Controller 10 - Álvaro Fernández Rojas <noltari@gmail.com> 11 - Jonas Gorski <jonas.gorski@gmail.com> 14 Broadcom BCM6328 SoC GPIO system controller which provides a register map 15 for controlling the GPIO and pins of the SoC. 18 "#address-cells": true [all …]
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/linux/arch/arm64/boot/dts/marvell/ |
H A D | cn9132-sr-cex7.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com> 7 #include <dt-bindings/gpio/gpio.h> 21 #include "armada-cp115.dtsi" 43 #include "armada-cp115.dtsi" 55 compatible = "solidrun,cn9132-sr-cex7", "marvell,cn9130"; 75 stdout-path = "serial0:115200n8"; 78 fan: pwm-fan { 79 compatible = "pwm-fan"; 80 cooling-levels = <0 51 102 153 204 255>; [all …]
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/linux/arch/arm/boot/dts/hisilicon/ |
H A D | hi3620-hi4511.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2012-2013 Linaro Ltd. 7 /dts-v1/; 13 compatible = "hisilicon,hi3620-hi4511"; 17 stdout-path = "serial0:115200n8"; 25 amba-bus { 31 pinctrl-names = "default", "sleep"; 32 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 33 pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; 38 pinctrl-names = "default", "sleep"; [all …]
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