Home
last modified time | relevance | path

Searched +full:gpio +full:- +full:cfg (Results 1 – 25 of 212) sorted by relevance

123456789

/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhi3620-hi4511.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Linaro Ltd.
7 /dts-v1/;
13 compatible = "hisilicon,hi3620-hi4511";
17 stdout-path = "serial0:115200n8";
25 amba-bus {
31 pinctrl-names = "default", "sleep";
32 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
33 pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
38 pinctrl-names = "default", "sleep";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dsemtech,sx1501q.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Semtech SX150x GPIO expander
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - semtech,sx1501q
17 - semtech,sx1502q
18 - semtech,sx1503q
19 - semtech,sx1504q
20 - semtech,sx1505q
[all …]
H A Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
26 samsung,pinctrl-wakeup-interrupt.yaml);
[all …]
H A Dnuvoton,wpcm450-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton WPCM450 pin control and GPIO
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
14 const: nuvoton,wpcm450-pinctrl
19 '#address-cells':
22 '#size-cells':
27 # 1. a GPIO controller node for each GPIO bank
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dwlf,wm8960.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dwm8903.txt7 - compatible : "wlf,wm8903"
9 - reg : the I2C address of the device.
11 - gpio-controller : Indicates this device is a GPIO controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and the
18 - interrupts : The interrupt line the codec is connected to.
20 - micdet-cfg : Default register value for R6 (Mic Bias). If absent, the
23 - micdet-delay : The debounce delay for microphone detection in mS. If
26 - gpio-cfg : A list of GPIO configuration register values. The list must
28 performed. If any entry has the value 0xffffffff, that GPIO's
31 - AVDD-supply : Analog power supply regulator on the AVDD pin.
[all …]
H A Dwm8960.txt7 - compatible : "wlf,wm8960"
9 - reg : the I2C address of the device.
12 - wlf,shared-lrclk: This is a boolean property. If present, the LRCM bit of
18 DACLRC pin. If shared-lrclk is present, no need to enable DAC for captrue.
20 - wlf,capless: This is a boolean property. If present, OUT3 pin will be
24 - wlf,hp-cfg: A list of headphone jack detect configuration register values.
26 hp-cfg[0]: HPSEL[1:0] of R48 (Additional Control 4).
27 hp-cfg[1]: {HPSWEN:HPSWPOL} of R24 (Additional Control 2).
28 hp-cfg[2]: {TOCLKSEL:TOEN} of R23 (Additional Control 1).
30 - wlf,gpio-cfg: A list of GPIO configuration register values.
[all …]
H A Dwlf,wm8903.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
30 - patches@opensource.cirrus.com
39 gpio-controller: true
40 '#gpio-cells':
46 micdet-cfg:
51 micdet-delay:
56 gpio-cfg:
57 $ref: /schemas/types.yaml#/definitions/uint32-array
[all …]
H A Dcs42l56.txt5 - compatible : "cirrus,cs42l56"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VCP-supply, VLDO-supply : power supplies for the device,
14 - cirrus,gpio-nreset : GPIO controller's phandle and the number
15 of the GPIO used to reset the codec.
17 - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
24 - cirrus,ain1a-ref-cfg, ain1b-ref-cfg : boolean, If present, AIN1A or AIN1B are configured
25 as a pseudo-differential input referenced to AIN1REF/AIN3A.
27 - cirrus,ain2a-ref-cfg, ain2b-ref-cfg : boolean, If present, AIN2A or AIN2B are configured
28 as a pseudo-differential input referenced to AIN2REF/AIN3B.
[all …]
H A Dcs42l52.txt5 - compatible : "cirrus,cs42l52"
7 - reg : the I2C address of the device for I2C
11 - cirrus,reset-gpio : GPIO controller's phandle and the number
12 of the GPIO used to reset the codec.
14 - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
21 - cirrus,mica-differential-cfg : boolean, If present, then the MICA input is configured
23 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
25 - cirrus,micb-differential-cfg : boolean, If present, then the MICB input is configured
27 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
29 - cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin
[all …]
H A Dwm8962.txt7 - compatible : "wlf,wm8962"
9 - reg : the I2C address of the device.
13 - clocks : The clock source of the mclk
15 - spk-mono: This is a boolean property. If present, the SPK_MONO bit
19 - mic-cfg : Default register value for R48 (Additional Control 4).
22 - gpio-cfg : A list of GPIO configuration register values. The list must
25 Any other value is regarded as setting the GPIO register by its reset
35 gpio-cfg = <
H A Dwlf,wm8962.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Wolfson WM8962 Ultra-Low Power Stereo CODEC
10 - patches@opensource.cirrus.com
13 - $ref: dai-common.yaml#
28 "#sound-dai-cells":
31 AVDD-supply:
34 CPVDD-supply:
37 DBVDD-supply:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhikey960-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/hisi.h>
12 range: gpio-range {
13 #pinctrl-single,gpio-range-cells = <3>;
17 compatible = "pinctrl-single";
19 #pinctrl-cells = <1>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
23 /* pin base, nr pins & gpio function */
[all …]
H A Dhikey970-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range {
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Draspberrypi_gpio.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org>
36 #include <sys/gpio.h>
43 #include <dev/gpio/gpiobusvar.h>
62 #define RPI_FW_GPIO_LOCK(_sc) sx_xlock(&(_sc)->sc_sx)
63 #define RPI_FW_GPIO_UNLOCK(_sc) sx_xunlock(&(_sc)->sc_sx)
66 {"raspberrypi,firmware-gpio", 1},
80 old_cfg.req.gpio = RPI_FW_GPIO_BASE + pin->gp_pin; in rpi_fw_gpio_pin_configure()
83 rv = bcm2835_firmware_property(sc->sc_firmware, in rpi_fw_gpio_pin_configure()
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dmax77620_gpio.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 #include <sys/gpio.h>
39 #include <dev/gpio/gpiobusvar.h>
43 MALLOC_DEFINE(M_MAX77620_GPIO, "MAX77620 gpio", "MAX77620 GPIO");
47 #define GPIO_LOCK(_sc) sx_slock(&(_sc)->gpio_lock)
48 #define GPIO_UNLOCK(_sc) sx_unlock(&(_sc)->gpio_lock)
49 #define GPIO_ASSERT(_sc) sx_assert(&(_sc)->gpio_lock, SA_LOCKED)
71 {"bias-pull-up", CFG_BIAS_PULL_UP},
72 {"bias-pull-down", CFG_BIAS_PULL_DOWN},
[all …]
/freebsd/sys/arm/nvidia/
H A Das3722_gpio.c1 /*-
30 #include <sys/gpio.h>
38 #include <dev/gpio/gpiobusvar.h>
42 MALLOC_DEFINE(M_AS3722_GPIO, "AS3722 gpio", "AS3722 GPIO");
71 #define GPIO_LOCK(_sc) sx_slock(&(_sc)->gpio_lock)
72 #define GPIO_UNLOCK(_sc) sx_unlock(&(_sc)->gpio_lock)
73 #define GPIO_ASSERT(_sc) sx_assert(&(_sc)->gpio_lock, SA_LOCKED)
85 {"bias-disable", AS3722_CFG_BIAS_DISABLE},
86 {"bias-pull-up", AS3722_CFG_BIAS_PULL_UP},
87 {"bias-pull-down", AS3722_CFG_BIAS_PULL_DOWN},
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cp
[all...]
H A Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-inpu
[all...]
H A Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
11 gpio@6000d000 {
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra30-lg-p895.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
11 pinctrl-names = "default";
12 pinctrl-0 = <&state_default>;
15 /* GNSS UART-B pinmux */
16 uartb-cts-rxd {
22 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
24 uartb-rts-txd {
30 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
/freebsd/lib/libgpio/
H A Dgpio.332 .Nd "library to handle GPIO pins"
47 .Fn gpio_pin_config "gpio_handle_t handle" "gpio_config_t *cfg"
51 .Fn gpio_pin_set_flags "gpio_handle_t handle" "gpio_config_t *cfg"
85 library provides an interface to configure GPIO pins.
92 When no more GPIO operations are needed, this handle can be destroyed
128 .Pa /usr/include/sys/gpio.h .
130 The get or set the state of a GPIO pin, the functions
162 .Bd -literal
178 .Bd -literal
179 gpio_config_t cfg;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
19 - items:
[all …]
/freebsd/sys/arm/ti/
H A Dti_pinmux.c34 * Exposes pinmux module to pinctrl-compatible interface
67 { -1, 0 }
73 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg))
75 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
77 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
79 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
82 * ti_padconf_devmap - Array of pins, should be defined one per SoC
91 * ti_pinmux_padconf_from_name - searches the list of pads and returns entry
103 padconf = ti_pinmux_dev->padconf; in ti_pinmux_padconf_from_name()
104 while (padconf->ballname != NULL) { in ti_pinmux_padconf_from_name()
[all …]
/freebsd/sys/dev/qcom_tlmm/
H A Dqcom_tlmm_pinmux.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
48 #include <sys/gpio.h>
52 #include <dev/gpio/gpiobusvar.h>
64 * For now we're hard-coded to doing IPQ4018 stuff here, but
73 { "bias-disable", PIN_ID_BIAS_DISABLE, 0 },
74 { "bias-high-impedance", PIN_ID_BIAS_HIGH_IMPEDANCE, 0 },
75 { "bias-bus-hold", PIN_ID_BIAS_BUS_HOLD, 0 },
76 { "bias-pull-up", PIN_ID_BIAS_PULL_UP, 0 },
77 { "bias-pull-down", PIN_ID_BIAS_PULL_DOWN, 0 },
[all …]

123456789