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/linux/virt/kvm/
H A Dpfncache.c28 struct gfn_to_pfn_cache *gpc; in gfn_to_pfn_cache_invalidate_start() local
31 list_for_each_entry(gpc, &kvm->gpc_list, list) { in gfn_to_pfn_cache_invalidate_start()
32 read_lock_irq(&gpc->lock); in gfn_to_pfn_cache_invalidate_start()
35 if (gpc->valid && !is_error_noslot_pfn(gpc->pfn) && in gfn_to_pfn_cache_invalidate_start()
36 gpc->uhva >= start && gpc->uhva < end) { in gfn_to_pfn_cache_invalidate_start()
37 read_unlock_irq(&gpc->lock); in gfn_to_pfn_cache_invalidate_start()
47 write_lock_irq(&gpc->lock); in gfn_to_pfn_cache_invalidate_start()
48 if (gpc in gfn_to_pfn_cache_invalidate_start()
73 kvm_gpc_check(struct gfn_to_pfn_cache * gpc,unsigned long len) kvm_gpc_check() argument
155 hva_to_pfn_retry(struct gfn_to_pfn_cache * gpc) hva_to_pfn_retry() argument
248 __kvm_gpc_refresh(struct gfn_to_pfn_cache * gpc,gpa_t gpa,unsigned long uhva) __kvm_gpc_refresh() argument
358 kvm_gpc_refresh(struct gfn_to_pfn_cache * gpc,unsigned long len) kvm_gpc_refresh() argument
377 kvm_gpc_init(struct gfn_to_pfn_cache * gpc,struct kvm * kvm) kvm_gpc_init() argument
389 __kvm_gpc_activate(struct gfn_to_pfn_cache * gpc,gpa_t gpa,unsigned long uhva,unsigned long len) __kvm_gpc_activate() argument
419 kvm_gpc_activate(struct gfn_to_pfn_cache * gpc,gpa_t gpa,unsigned long len) kvm_gpc_activate() argument
431 kvm_gpc_activate_hva(struct gfn_to_pfn_cache * gpc,unsigned long uhva,unsigned long len) kvm_gpc_activate_hva() argument
439 kvm_gpc_deactivate(struct gfn_to_pfn_cache * gpc) kvm_gpc_deactivate() argument
[all...]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgv100.c28 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_gr_trap_sm() argument
32 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); in gv100_gr_trap_sm()
33 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); in gv100_gr_trap_sm()
40 nvkm_error(subdev, "GPC%i/TPC%i/SM%d trap: " in gv100_gr_trap_sm()
42 gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : ""); in gv100_gr_trap_sm()
44 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000); in gv100_gr_trap_sm()
45 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); in gv100_gr_trap_sm()
49 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) in gv100_gr_trap_mp() argument
51 gv100_gr_trap_sm(gr, gpc, tpc, 0); in gv100_gr_trap_mp()
52 gv100_gr_trap_sm(gr, gpc, tpc, 1); in gv100_gr_trap_mp()
[all …]
H A Dctxgp100.c52 int gpc, ppc, n = 0; in gp100_grctx_generate_attrib() local
58 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp100_grctx_generate_attrib()
60 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
63 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp100_grctx_generate_attrib()
65 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp100_grctx_generate_attrib()
74 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
97 int gpc; in gp100_grctx_generate_attrib_cb_size() local
99 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp100_grctx_generate_attrib_cb_size()
114 const u8 gpc = gr->sm[sm].gpc; in gp100_grctx_generate_smid_config() local
116 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); in gp100_grctx_generate_smid_config()
[all …]
H A Dctxgp102.c51 int gpc, ppc, n = 0; in gp102_grctx_generate_attrib() local
57 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_grctx_generate_attrib()
59 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
63 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp102_grctx_generate_attrib()
64 const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); in gp102_grctx_generate_attrib()
66 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp102_grctx_generate_attrib()
76 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
90 int gpc; in gp102_grctx_generate_attrib_cb_size() local
92 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp102_grctx_generate_attrib_cb_size()
H A Dctxgm200.c55 const u8 gpc = gr->sm[sm].gpc; in gm200_grctx_generate_smid_config() local
57 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); in gm200_grctx_generate_smid_config()
58 gpcs[gpc] |= sm << (tpc * 8); in gm200_grctx_generate_smid_config()
87 int gpc, ppc, i; in gm200_grctx_generate_dist_skip_table() local
89 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm200_grctx_generate_dist_skip_table()
91 u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
92 u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
95 ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
96 ((u8 *)data)[gpc] |= ppc_tpcm; in gm200_grctx_generate_dist_skip_table()
H A Dctxgv100.c73 int gpc, ppc, n = 0; in gv100_grctx_generate_attrib() local
79 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_grctx_generate_attrib()
81 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
85 const u32 o = PPC_UNIT(gpc, ppc, 0); in gv100_grctx_generate_attrib()
87 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gv100_grctx_generate_attrib()
96 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
160 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_grctx_generate_sm_id() argument
164 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc); in gv100_grctx_generate_sm_id()
166 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in gv100_grctx_generate_sm_id()
167 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); in gv100_grctx_generate_sm_id()
[all …]
H A Dtu102.c45 int tpc = gv100_gr_nonpes_aware_tpc(gr, gr->sm[sm].gpc, gr->sm[sm].tpc); in tu102_gr_init_fs()
47 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + tpc * 4), sm); in tu102_gr_init_fs()
60 u8 bank[GPC_MAX] = {}, gpc, i, j; in tu102_gr_init_zcull() local
71 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in tu102_gr_init_zcull()
72 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in tu102_gr_init_zcull()
73 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in tu102_gr_init_zcull()
74 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in tu102_gr_init_zcull()
76 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in tu102_gr_init_zcull()
H A Dgf117.c131 u8 bank[GPC_MAX] = {}, gpc, i, j; in gf117_gr_init_zcull() local
142 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_gr_init_zcull()
143 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gf117_gr_init_zcull()
144 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in gf117_gr_init_zcull()
145 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf117_gr_init_zcull()
147 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf117_gr_init_zcull()
H A Dctxgf117.c254 int gpc, ppc; in gf117_grctx_generate_attrib() local
259 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_grctx_generate_attrib()
261 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
262 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
264 const u32 o = PPC_UNIT(gpc, ppc, 0); in gf117_grctx_generate_attrib()
266 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gf117_grctx_generate_attrib()
270 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
272 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
H A Dgp102.c89 u32 mask = 0, data, gpc; in gp102_gr_init_swdx_pes_mask() local
91 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_gr_init_swdx_pes_mask()
92 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; in gp102_gr_init_swdx_pes_mask()
93 mask |= data << (gpc * 4); in gp102_gr_init_swdx_pes_mask()
H A Dctxtu102.c34 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in tu102_grctx_generate_sm_id() argument
38 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc); in tu102_grctx_generate_sm_id()
40 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in tu102_grctx_generate_sm_id()
41 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); in tu102_grctx_generate_sm_id()
H A Dctxgf100.c1037 int gpc, tpc; in gf100_grctx_generate_attrib() local
1042 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_attrib()
1043 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf100_grctx_generate_attrib()
1044 const u32 o = TPC_UNIT(gpc, tpc, 0x0520); in gf100_grctx_generate_attrib()
1084 data |= gr->sm[sm++].gpc << (j * 8); in gf100_grctx_generate_r4060a8()
1253 int i, gpc; in gf100_grctx_generate_alpha_beta_tables() local
1265 for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
1266 if (abits[gpc] < gr->tpc_nr[gpc]) { in gf100_grctx_generate_alpha_beta_tables()
1267 abits[gpc]++; in gf100_grctx_generate_alpha_beta_tables()
1273 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
[all …]
H A Dctxga102.c25 ga102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in ga102_grctx_generate_sm_id() argument
29 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc); in ga102_grctx_generate_sm_id()
31 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in ga102_grctx_generate_sm_id()
/linux/Documentation/devicetree/bindings/power/
H A Dfsl,imx-gpcv2.yaml13 The i.MX7S/D General Power Control (GPC) block contains Power Gating
16 Power domains contained within GPC node are generic power domain
27 - fsl,imx7d-gpc
28 - fsl,imx8mn-gpc
29 - fsl,imx8mq-gpc
30 - fsl,imx8mm-gpc
31 - fsl,imx8mp-gpc
68 include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
69 include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
70 include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
[all …]
/linux/arch/mips/boot/dts/ingenic/
H A Dqi_lb60.dts114 col-gpios = <&gpc 10 0>, <&gpc 11 0>, <&gpc 12 0>, <&gpc 13 0>,
115 <&gpc 14 0>, <&gpc 15 0>, <&gpc 16 0>, <&gpc 17 0>;
186 sck-gpios = <&gpc 23 GPIO_ACTIVE_HIGH>;
187 mosi-gpios = <&gpc 22 GPIO_ACTIVE_HIGH>;
188 cs-gpios = <&gpc 21 GPIO_ACTIVE_LOW>;
196 status-gpios = <&gpc 27 GPIO_ACTIVE_LOW>;
268 rb-gpios = <&gpc 30 GPIO_ACTIVE_HIGH>;
H A Drs90.dts59 gpios = <&gpc 10 GPIO_ACTIVE_LOW>;
65 gpios = <&gpc 11 GPIO_ACTIVE_LOW>;
83 gpios = <&gpc 31 GPIO_ACTIVE_LOW>;
89 gpios = <&gpc 30 GPIO_ACTIVE_LOW>;
95 gpios = <&gpc 12 GPIO_ACTIVE_LOW>;
128 enable-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
236 cd-gpios = <&gpc 20 GPIO_ACTIVE_LOW>;
266 rb-gpios = <&gpc 27 GPIO_ACTIVE_HIGH>;
H A Dcu1000-neo.dts37 reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>;
72 cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>;
87 interrupt-parent = <&gpc>;
146 interrupt-parent = <&gpc>;
163 snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
/linux/drivers/irqchip/
H A Dirq-imx-gpcv2.c197 { .compatible = "fsl,imx7d-gpc", .data = (const void *) 2 },
198 { .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
238 pr_err("%pOF: unable to map gpc registers\n", node); in imx_gpcv2_irqchip_init()
268 /* Let CORE0 as the default CPU to wake up by GPC */ in imx_gpcv2_irqchip_init()
283 * later the GPC power domain driver will not be skipped. in imx_gpcv2_irqchip_init()
290 IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
291 IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);
/linux/arch/arm/boot/dts/samsung/
H A Ds3c64xx-pinctrl.dtsi33 gpc: gpc-gpio-bank { label
214 samsung,pins = "gpc-0", "gpc-1", "gpc-2";
220 samsung,pins = "gpc-3";
226 samsung,pins = "gpc-4", "gpc-5", "gpc-6";
232 samsung,pins = "gpc-7";
305 samsung,pins = "gpc-4";
311 samsung,pins = "gpc-5";
354 samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",
/linux/arch/arm/mach-imx/
H A Dgpc.c67 /* Tell GPC to power off ARM core when suspend */ in imx_gpc_pre_suspend()
160 .name = "GPC",
262 * later the GPC power domain driver will not be skipped. in imx_gpc_init()
268 IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
274 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); in imx_gpc_check_dt()
281 /* map GPC, so that at least CPUidle and WARs keep working */ in imx_gpc_check_dt()
H A Dcpu-imx5.c130 u32 gpc; in imx5_pmu_init() local
152 gpc = readl_relaxed(tigerp_base + ARM_GPC); in imx5_pmu_init()
153 gpc |= DBGEN; in imx5_pmu_init()
154 writel_relaxed(gpc, tigerp_base + ARM_GPC); in imx5_pmu_init()
/linux/drivers/pmdomain/imx/
H A Dimx8m-blk-ctrl.c113 /* power up upstream GPC domain */ in imx8m_blk_ctrl_power_on()
158 /* power down upstream GPC domain */ in imx8m_blk_ctrl_power_off()
287 * We use runtime PM to trigger power on/off of the upstream GPC in imx8m_blk_ctrl_probe()
365 * control the upstream GPC domains. Things happen in the right order in imx8m_blk_ctrl_suspend()
426 * allow the handshake with the GPC to progress we put the VPUs in imx8mm_vpu_power_notifier()
434 * On power up we have no software backchannel to the GPC to in imx8mm_vpu_power_notifier()
436 * bit. On power down the GPC driver waits for the handshake. in imx8mm_vpu_power_notifier()
538 * On power up we have no software backchannel to the GPC to in imx8mm_disp_power_notifier()
540 * bit. On power down the GPC driver waits for the handshake. in imx8mm_disp_power_notifier()
608 * On power up we have no software backchannel to the GPC to in imx8mn_disp_power_notifier()
[all …]
H A Dgpc.c75 /* Request GPC to power down domain */ in imx6_pm_domain_power_off()
111 /* Request GPC to power up domain */ in imx6_pm_domain_power_on()
320 { .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
321 { .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
322 { .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
323 { .compatible = "fsl,imx6sx-gpc", .data = &imx6sx_dt_data },
544 .name = "imx-gpc",
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
H A Dgpc.fuc1 /* fuc microcode for gf100 PGRAPH/GPC
112 // GPC fuc initialisation, executed by triggering ucode start, will
122 // 31:0: GPC context size
158 // determine which GPC we are, setup (optional) mmio access offset
190 clear b32 $r3 // track GPC context size here
198 // calculate GPC mmio context size
367 // Set this GPC's bit in HUB_BAR, used to signal completion of various
395 // Transfer GPC context data between GPU and storage area
/linux/Documentation/devicetree/bindings/dma/
H A Dnvidia,tegra186-gpc-dma.yaml4 $id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
7 title: NVIDIA Tegra GPC DMA Controller
10 The Tegra General Purpose Central (GPC) DMA controller is used for faster

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