| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx_gmu.c | 22 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
24 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
29 gmu->hung = true; in a6xx_gmu_fault()
40 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
43 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
44 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
47 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
49 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
53 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
56 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
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| H A D | a6xx_hfi.c | 31 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
47 * If we are to assume that the GMU firmware is in fact a rational actor in a6xx_hfi_queue_read()
62 if (!gmu->legacy) in a6xx_hfi_queue_read()
72 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
96 if (!gmu->legacy) { in a6xx_hfi_queue_write()
107 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
111 static int a6xx_hfi_wait_for_msg_interrupt(struct a6xx_gmu *gmu, u32 id, u32 seqnum) in a6xx_hfi_wait_for_msg_interrupt() argument
115 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_hfi_wait_for_msg_interrupt()
119 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_msg_interrupt()
128 /* We may timeout because the GMU is temporarily wedged from in a6xx_hfi_wait_for_msg_interrupt()
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| H A D | a6xx_gpu.c | 27 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H); in a6xx_gmu_get_timestamp()
28 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L); in a6xx_gmu_get_timestamp()
29 temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H); in a6xx_gmu_get_timestamp()
31 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); in a6xx_gmu_get_timestamp()
32 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); in a6xx_gmu_get_timestamp()
33 temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); in a6xx_gmu_get_timestamp()
62 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in fenced_write() local
67 /* Nothing else to be done in the case of no-GMU */ in fenced_write()
76 if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, in fenced_write()
84 if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, in fenced_write()
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| H A D | a8xx_gpu.c | 135 /* Check that the GMU is idle */ in _a8xx_check_idle()
136 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a8xx_check_idle()
200 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a8xx_set_hwcg() local
206 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, in a8xx_set_hwcg()
208 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, in a8xx_set_hwcg()
210 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, in a8xx_set_hwcg()
228 * GMU enables clk gating in GBIF during boot up. So, in a8xx_set_hwcg()
625 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
631 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
676 gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1, in hw_init()
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| H A D | a6xx_gpu_state.c | 157 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
1211 /* Read a block of GMU registers */
1220 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
1240 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
1242 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
1263 /* Get the CX GMU registers from AHB */ in a6xx_get_gmu_registers()
1283 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_get_gmu_registers()
1317 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
1320 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
1322 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_snapshot_gmu_hfi_history()
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| H A D | adreno_gpu.c | 340 /* Let any concurrent GMU transactions know that the MMU may be in adreno_fault_handler()
626 /* Skip loading GMU firmware with GMU Wrapper */ in adreno_load_fw()
1212 /* Only handle the core clock when GMU is not in use (or is absent). */ in adreno_gpu_init()
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| H A D | a6xx_gpu_state.h | 345 /* GMU GX */
354 /* GMU CX */
364 /* GMU AO */
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| /linux/Documentation/devicetree/bindings/display/msm/ |
| H A D | gmu.yaml | 6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
9 title: GMU attached to certain Adreno GPUs
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
24 - pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28 - const: qcom,adreno-gmu
29 - const: qcom,adreno-gmu-wrapper
49 - description: GMU HFI interrupt
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| H A D | gpu.yaml | 126 qcom,gmu:
129 For GMU attached devices a phandle to the GMU device that will
373 - const: gmu
374 description: CX GMU clock
457 then: # Starting with A6xx, the clocks are usually defined in the GMU node
514 // Example a6xx (with GMU):
551 qcom,gmu = <&gmu>;
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| /linux/drivers/clk/qcom/ |
| H A D | gdsc.c | 696 * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
701 * the GMU crashes it could leave the GX on. In order to successfully bring back
710 * driver. During power up, nothing will happen from the CPU (and the GMU will
731 * is managed by the GMU firmware, and high level OS must not attempt
732 * to disable it. The only exception is during GMU recovery, where the
733 * GMU driver can set GenPD’s synced_poweroff flag to allow explicitly
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| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | purwa.dtsi | 50 &gmu {
51 compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
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| H A D | sc8280xp.dtsi | 3403 qcom,gmu = <&gmu>;
3467 gmu: gmu@3d6a000 { label
3468 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
3472 reg-names = "gmu", "rscc", "gmu_pdc";
3475 interrupt-names = "hfi", "gmu";
3483 clock-names = "gmu",
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| H A D | monaco.dtsi | 4964 qcom,gmu = <&gmu>;
5012 gmu: gmu@3d6a000 { label
5013 compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu";
5017 reg-names = "gmu", "rscc", "gmu_pdc";
5020 interrupt-names = "hfi", "gmu";
5027 clock-names = "gmu",
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| H A D | sm8650.dtsi | 4212 qcom,gmu = <&gmu>;
4309 gmu: gmu@3d6a000 { label
4310 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
4314 reg-names = "gmu", "rscc", "gmu_pdc";
4318 interrupt-names = "hfi", "gmu";
4328 "gmu",
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| H A D | glymur.dtsi | 3837 qcom,gmu = <&gmu>;
3957 gmu: gmu@3d6c000 { label
3958 compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu";
3961 reg-names = "gmu";
3966 "gmu";
3975 "gmu",
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| /linux/Documentation/devicetree/bindings/sram/ |
| H A D | qcom,ocmem.yaml | 120 gmu-sram@0 {
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| /linux/drivers/gpu/drm/msm/ |
| H A D | msm_gem.h | 44 * A VM object representing a GPU (or display or GMU or ...) virtual address
|