Home
last modified time | relevance | path

Searched full:gmii (Results 1 – 25 of 126) sorted by relevance

123456

/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-gmii-sel.yaml5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
26 | |Port 1..<--+-->GMII/MII<------->
51 - ti,am3352-phy-gmii-sel
52 - ti,dra7xx-phy-gmii-sel
53 - ti,am43xx-phy-gmii-sel
54 - ti,dm814-phy-gmii-sel
55 - ti,am654-phy-gmii-sel
56 - ti,j7200-cpsw5g-phy-gmii-sel
57 - ti,j721e-cpsw9g-phy-gmii-sel
58 - ti,j784s4-cpsw9g-phy-gmii-sel
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,gmii-to-rgmii.yaml4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
7 title: Xilinx GMII to RGMII Converter
13 The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media
24 const: xlnx,gmii-to-rgmii-1.0
55 compatible = "xlnx,gmii-to-rgmii-1.0";
H A Dsocfpga-dwmac.txt32 - compatible : Should be altr,gmii-to-sgmii-2.0
38 compatible = "altr,gmii-to-sgmii-2.0";
56 altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
H A Dcpsw-phy-sel.txt21 reg-names = "gmii-sel";
28 reg-names = "gmii-sel";
H A Dsnps,dwc-qos-ethernet.txt29 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
34 In some configurations (e.g. GMII/RGMII), this clock is derived from the
146 phy-mode = "gmii";
H A Dmicrochip,lan966x-switch.yaml98 - gmii
158 phy-mode = "gmii";
H A Dqca,ar71xx.yaml97 phy-mode = "gmii";
128 phy-mode = "gmii";
H A Dti,cpsw-switch.yaml16 gigabit media independent interface (GMII),reduced gigabit media
104 description: phandle on phy-gmii-sel PHY
H A Dti,dp83867.yaml25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
/linux/drivers/phy/ti/
H A Dphy-gmii-sel.c260 .compatible = "ti,am3352-phy-gmii-sel",
264 .compatible = "ti,dra7xx-phy-gmii-sel",
268 .compatible = "ti,am43xx-phy-gmii-sel",
272 .compatible = "ti,dm814-phy-gmii-sel",
276 .compatible = "ti,am654-phy-gmii-sel",
280 .compatible = "ti,j7200-cpsw5g-phy-gmii-sel",
284 .compatible = "ti,j721e-cpsw9g-phy-gmii-sel",
288 .compatible = "ti,j784s4-cpsw9g-phy-gmii-sel",
533 .name = "phy-gmii-sel",
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_vt.dts40 phy-mode = "gmii";
76 phy-mode = "gmii";
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k2000-ref.dts65 phy-mode = "gmii";
80 phy-mode = "gmii";
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-ns2502.dts108 pinctrl-gmii {
110 function = "gmii";
H A Dgemini-ssi1328.dts118 pinctrl-gmii {
121 function = "gmii";
H A Dgemini-wbd222.dts114 pinctrl-gmii {
117 function = "gmii";
H A Dgemini-nas4220b.dts103 pinctrl-gmii {
105 function = "gmii";
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-rgmii.c29 * Functions for RGMII/GMII/MII initialization, configuration,
50 * Returns Number of RGMII/GMII/MII ports (0-4).
68 * GMII/MII mode. This limits us to 2 ports in __cvmx_helper_rgmii_probe()
411 * 1 1 1 X Port 1: GMII/MII; Port 2: disabled. GMII or in __cvmx_helper_rgmii_link_set()
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-socfpga.c153 "altr,gmii-to-sgmii-converter", 0); in socfpga_dwmac_parse_data()
285 /* Overwrite val to GMII if splitter core is enabled. The phymode here in socfpga_gen5_set_phy_mode()
287 * EMAC core is GMII. in socfpga_gen5_set_phy_mode()
341 /* Overwrite val to GMII if splitter core is enabled. The phymode here in socfpga_gen10_set_phy_mode()
343 * EMAC core is GMII. in socfpga_gen10_set_phy_mode()
/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-pcb8291.dts111 phy-mode = "gmii";
118 phy-mode = "gmii";
H A Dlan966x-pcb8309.dts180 phy-mode = "gmii";
187 phy-mode = "gmii";
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi157 phy-mode = "gmii";
164 phy-mode = "gmii";
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt50 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
66 phy-connection-type = "gmii";
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-helper-rgmii.h31 * Functions for RGMII/GMII/MII initialization, configuration,
43 * Returns Number of RGMII/GMII/MII ports (0-4).
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-tysom-m.dts84 phy-mode = "gmii";
91 phy-mode = "gmii";
H A Dmpfs-m100pfsevp.dts91 phy-mode = "gmii";
100 phy-mode = "gmii";

123456