Home
last modified time | relevance | path

Searched +full:gmii +full:- +full:to +full:- +full:sgmii +full:- +full:converter (Results 1 – 5 of 5) sorted by relevance

/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A Dreg_addr_bb.h4 * The contents of this file are subject to the terms of the
9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
30 * at http://opensource.org/licenses/CDDL-1.0
40 … (0x1<<0) // Signals an unknown address to the rf module.
50 … (0x1<<0) // Signals an unknown address to the rf module.
55 … (0x1<<0) // Signals an unknown address to the rf module.
60 … 0x001d14UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
61 … line) in the selected line (before shift).for selecting a line to output
[all …]
H A Dreg_addr_k2.h4 * The contents of this file are subject to the terms of the
9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
30 * at http://opensource.org/licenses/CDDL-1.0
40 … (0x1<<0) // Signals an unknown address to the rf module.
50 … (0x1<<0) // Signals an unknown address to the rf module.
55 … (0x1<<0) // Signals an unknown address to the rf module.
60 … 0x001d14UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
61 … line) in the selected line (before shift).for selecting a line to output
[all …]
H A Dreg_addr_e5.h4 * The contents of this file are subject to the terms of the
9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
30 * at http://opensource.org/licenses/CDDL-1.0
40 … (0x1<<0) // Signals an unknown address to the rf module.
50 … (0x1<<0) // Signals an unknown address to the rf module.
55 … (0x1<<0) // Signals an unknown address to the rf module.
60 … 0x001d14UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
61 … line) in the selected line (before shift).for selecting a line to output
[all …]
H A Dreg_addr_ah_compile15.h4 * The contents of this file are subject to the terms of the
9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
30 * at http://opensource.org/licenses/CDDL-1.0
40 … (0x1<<0) // Signals an unknown address to the rf module.
50 … (0x1<<0) // Signals an unknown address to the rf module.
55 … (0x1<<0) // Signals an unknown address to the rf module.
60 … 0x001d14UL //Access:RW DataWidth:0x8 DBMUX register for selecting a line to output Chips: K2
61 … in the selected line (before shift).for selecting a line to output Chips: K2
[all …]
H A Dreg_addr.h4 * The contents of this file are subject to the terms of the
9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
30 * at http://opensource.org/licenses/CDDL-1.0
40 … (0x1<<0) // Signals an unknown address to the rf module.
50 … (0x1<<0) // Signals an unknown address to the rf module.
55 … (0x1<<0) // Signals an unknown address to the rf module.
60 … 0x001d14UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
61 … line) in the selected line (before shift).for selecting a line to output
[all …]