Home
last modified time | relevance | path

Searched +full:gmii +full:- +full:to +full:- +full:sgmii +full:- +full:converter (Results 1 – 6 of 6) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/net/
H A Daltr,gmii-to-sgmii-2.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/net/altr,gmii-to-sgmii-2.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Altera GMII to SGMII Converter
11 - Matthew Gerlach <matthew.gerlach@altera.com>
14 This binding describes the Altera GMII to SGMII converter.
18 const: altr,gmii-to-sgmii-2.0
22 - description: Registers for the emac splitter IP
23 - description: Registers for the GMII to SGMII converter.
[all …]
H A Dsocfpga-dwmac.txt9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
18 bit for each emac to enable/disable signals from the FPGA fabric to the
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
26 phy-mode: The phy mode the ethernet operates in
27 altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
29 This device node has additional phandle dependency, the sgmii converter:
[all …]
H A Daltr,socfpga-stmmac.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthew Gerlach <matthew.gerlach@altera.com>
16 # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
24 - altr,socfpga-stmmac
25 - altr,socfpga-stmmac-a10-s10
26 - altr,socfpga-stmmac-agilex5
29 - compatible
[all …]
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
23 - snps,dwmac
24 - snps,dwmac-3.40a
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
420 /* [0x4c] XGMII 32 to 64 data FIFO control */
424 /* [0x54] XGMII 64 to 32 data FIFO control */
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
621 * [0x84] SERDES 32-bit interface bit selection
625 * [0x88] SERDES 32-bit interface bit selection
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 … (0x1<<0) // Signals an unknown address to the rf module.
43 … (0x1<<0) // Signals an unknown address to the rf module.
48 … (0x1<<0) // Signals an unknown address to the rf module.
53 … 0x001d14UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
54 … line) in the selected line (before shift).for selecting a line to output
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
[all …]