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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v2_1.c144 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_1_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_1_init_gart_aperture_regs()
149 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_1_init_gart_aperture_regs()
151 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_1_init_gart_aperture_regs()
163 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_1_init_system_aperture_regs()
164 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_1_init_system_aperture_regs()
168 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_1_init_system_aperture_regs()
170 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_1_init_system_aperture_regs()
239 if (adev->gmc.translate_further) { in gfxhub_v2_1_init_cache_regs()
326 !adev->gmc.noretry); in gfxhub_v2_1_setup_vmid_config()
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H A Damdgpu_gmc.c53 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; in amdgpu_gmc_pdb0_alloc()
54 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; in amdgpu_gmc_pdb0_alloc()
67 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
71 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); in amdgpu_gmc_pdb0_alloc()
75 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gmc_pdb0_alloc()
78 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); in amdgpu_gmc_pdb0_alloc()
82 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
86 amdgpu_bo_unpin(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
88 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
90 amdgpu_bo_unref(&adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
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H A Dgmc_v9_0.c760 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
761 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; in gmc_v9_0_set_irq_funcs()
764 !adev->gmc.xgmi.connected_to_cpu && in gmc_v9_0_set_irq_funcs()
765 !adev->gmc.is_app_apu) { in gmc_v9_0_set_irq_funcs()
766 adev->gmc.ecc_irq.num_types = 1; in gmc_v9_0_set_irq_funcs()
767 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; in gmc_v9_0_set_irq_funcs()
877 spin_lock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
939 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
1113 if (!adev->gmc.translate_further) in gmc_v9_0_get_vm_pde()
1167 adev->gmc.xgmi.connected_to_cpu) in gmc_v9_0_get_coherence_flags()
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H A Dgmc_v10_0.c200 adev->gmc.vm_fault.num_types = 1; in gmc_v10_0_set_irq_funcs()
201 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; in gmc_v10_0_set_irq_funcs()
204 adev->gmc.ecc_irq.num_types = 1; in gmc_v10_0_set_irq_funcs()
205 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; in gmc_v10_0_set_irq_funcs()
286 spin_lock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_gpu_tlb()
332 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_gpu_tlb()
501 if (!adev->gmc.translate_further) in gmc_v10_0_get_vm_pde()
581 if (adev->gmc.gmc_funcs == NULL) in gmc_v10_0_set_gmc_funcs()
582 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; in gmc_v10_0_set_gmc_funcs()
646 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v10_0_early_init()
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H A Dgmc_v8_0.c35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
262 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v8_0_init_microcode()
266 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_init_microcode()
295 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
298 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
301 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
304 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
307 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
364 if (!adev->gmc.fw) in gmc_v8_0_polaris_mc_load_microcode()
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H A Dgmc_v11_0.c169 adev->gmc.vm_fault.num_types = 1; in gmc_v11_0_set_irq_funcs()
170 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; in gmc_v11_0_set_irq_funcs()
173 adev->gmc.ecc_irq.num_types = 1; in gmc_v11_0_set_irq_funcs()
174 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; in gmc_v11_0_set_irq_funcs()
247 spin_lock(&adev->gmc.invalidate_lock); in gmc_v11_0_flush_gpu_tlb()
298 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v11_0_flush_gpu_tlb()
465 if (!adev->gmc.translate_further) in gmc_v11_0_get_vm_pde()
545 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; in gmc_v11_0_set_gmc_funcs()
617 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v11_0_early_init()
618 adev->gmc.shared_aperture_end = in gmc_v11_0_early_init()
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H A Dgmc_v7_0.c40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
160 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v7_0_init_microcode()
164 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v7_0_init_microcode()
185 if (!adev->gmc.fw) in gmc_v7_0_mc_load_microcode()
188 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v7_0_mc_load_microcode()
191 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v7_0_mc_load_microcode()
194 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
197 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
294 adev->gmc.vram_start >> 12); in gmc_v7_0_mc_program()
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H A Dgmc_v12_0.c162 adev->gmc.vm_fault.num_types = 1; in gmc_v12_0_set_irq_funcs()
163 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; in gmc_v12_0_set_irq_funcs()
166 adev->gmc.ecc_irq.num_types = 1; in gmc_v12_0_set_irq_funcs()
167 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; in gmc_v12_0_set_irq_funcs()
216 spin_lock(&adev->gmc.invalidate_lock); in gmc_v12_0_flush_vm_hub()
275 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v12_0_flush_vm_hub()
482 adev->gmc.vram_start; in gmc_v12_0_get_vm_pde()
485 if (!adev->gmc.translate_further) in gmc_v12_0_get_vm_pde()
579 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; in gmc_v12_0_set_gmc_funcs()
632 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v12_0_early_init()
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H A Dgfxhub_v1_0.c58 if (adev->gmc.pdb0_bo) in gfxhub_v1_0_init_gart_aperture_regs()
59 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_0_init_gart_aperture_regs()
68 if (adev->gmc.pdb0_bo) { in gfxhub_v1_0_init_gart_aperture_regs()
70 (u32)(adev->gmc.fb_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
72 (u32)(adev->gmc.fb_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
75 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
85 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
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H A Dgfxhub_v1_2.c80 if (adev->gmc.pdb0_bo) in gfxhub_v1_2_xcc_init_gart_aperture_regs()
81 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
91 if (adev->gmc.pdb0_bo) { in gfxhub_v1_2_xcc_init_gart_aperture_regs()
94 (u32)(adev->gmc.fb_start >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
97 (u32)(adev->gmc.fb_start >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
101 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
104 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
108 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
111 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
115 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
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H A Dgmc_v6_0.c38 #include "gmc/gmc_6_0_d.h"
39 #include "gmc/gmc_6_0_sh_mask.h"
134 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v6_0_init_microcode()
140 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v6_0_init_microcode()
153 if (!adev->gmc.fw) in gmc_v6_0_mc_load_microcode()
156 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v6_0_mc_load_microcode()
160 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v6_0_mc_load_microcode()
163 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
166 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
257 adev->gmc.vram_start >> 12); in gmc_v6_0_mc_program()
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H A Dmmhub_v1_8.c48 adev->gmc.fb_start = base; in mmhub_v1_8_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_8_get_fb_location()
82 if (adev->gmc.pdb0_bo) in mmhub_v1_8_init_gart_aperture_regs()
83 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in mmhub_v1_8_init_gart_aperture_regs()
94 if (adev->gmc.pdb0_bo) { in mmhub_v1_8_init_gart_aperture_regs()
97 (u32)(adev->gmc.fb_start >> 12)); in mmhub_v1_8_init_gart_aperture_regs()
100 (u32)(adev->gmc.fb_start >> 44)); in mmhub_v1_8_init_gart_aperture_regs()
104 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_8_init_gart_aperture_regs()
107 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_8_init_gart_aperture_regs()
112 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_8_init_gart_aperture_regs()
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H A Dgfxhub_v1_1.c88 if (max_region || adev->gmc.xgmi.connected_to_cpu) { in gfxhub_v1_1_get_xgmi_info()
89 adev->gmc.xgmi.num_physical_nodes = max_region + 1; in gfxhub_v1_1_get_xgmi_info()
91 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) in gfxhub_v1_1_get_xgmi_info()
95 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
99 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
104 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) in gfxhub_v1_1_get_xgmi_info()
107 adev->gmc.xgmi.node_segment_size = seg_size; in gfxhub_v1_1_get_xgmi_info()
H A Damdgpu_gmc.h84 * GMC page fault information
372 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((…
373 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping(…
374 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
375 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (l…
376 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapp…
378 (adev)->gmc.gmc_funcs->override_vm_pte_flags \
380 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
383 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \
394 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) in amdgpu_gmc_vram_full_visible() argument
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H A Dmmhub_v1_0.c48 adev->gmc.fb_start = base; in mmhub_v1_0_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_0_get_fb_location()
75 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v1_0_init_system_aperture_regs()
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v1_0_init_system_aperture_regs()
97 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v1_0_init_system_aperture_regs()
109 max((adev->gmc.fb_end >> 18) + 0x1, in mmhub_v1_0_init_system_aperture_regs()
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H A Dgfxhub_v12_0.c148 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
153 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
155 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
164 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v12_0_init_system_aperture_regs()
165 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v12_0_init_system_aperture_regs()
169 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v12_0_init_system_aperture_regs()
171 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v12_0_init_system_aperture_regs()
174 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start in gfxhub_v12_0_init_system_aperture_regs()
242 if (adev->gmc.translate_further) { in gfxhub_v12_0_init_cache_regs()
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H A Damdgpu_amdkfd.c229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; in amdgpu_amdkfd_device_init()
240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; in amdgpu_amdkfd_device_fini_sw()
456 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) in amdgpu_amdkfd_get_local_mem_info()
466 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
467 mem_info->local_mem_size_private = adev->gmc.real_vram_size - in amdgpu_amdkfd_get_local_mem_info()
468 adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
470 mem_info->vram_width = adev->gmc.vram_width; in amdgpu_amdkfd_get_local_mem_info()
473 &adev->gmc.aper_base, in amdgpu_amdkfd_get_local_mem_info()
567 adev->gmc.xgmi.physical_node_id, in amdgpu_amdkfd_get_xgmi_hops_count()
568 peer_adev->gmc.xgmi.physical_node_id, ret); in amdgpu_amdkfd_get_xgmi_hops_count()
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H A Dgfxhub_v11_5_0.c145 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
152 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
160 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
165 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v11_5_0_init_system_aperture_regs()
168 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v11_5_0_init_system_aperture_regs()
237 if (adev->gmc.translate_further) { in gfxhub_v11_5_0_init_cache_regs()
364 adev->gmc.vram_start >> 24); in gfxhub_v11_5_0_gart_enable()
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H A Dgfxhub_v3_0.c140 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_init_system_aperture_regs()
157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
234 if (adev->gmc.translate_further) { in gfxhub_v3_0_init_cache_regs()
361 adev->gmc.vram_start >> 24); in gfxhub_v3_0_gart_enable()
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H A Dgfxhub_v2_0.c141 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
143 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_0_init_system_aperture_regs()
159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_0_init_system_aperture_regs()
163 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
165 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
233 if (adev->gmc.translate_further) { in gfxhub_v2_0_init_cache_regs()
314 !adev->gmc.noretry); in gfxhub_v2_0_setup_vmid_config()
H A Dmmhub_v3_3.c155 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_3_init_gart_aperture_regs()
157 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_3_init_gart_aperture_regs()
160 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_3_init_gart_aperture_regs()
162 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_3_init_gart_aperture_regs()
172 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_3_init_system_aperture_regs()
173 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_3_init_system_aperture_regs()
182 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_3_init_system_aperture_regs()
184 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_3_init_system_aperture_regs()
249 if (adev->gmc.translate_further) { in mmhub_v3_3_init_cache_regs()
378 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_3_init_saw_regs()
[all …]
H A Daqua_vanjaram.c497 (adev->gmc.supported_nps_modes & nps_modes); in aqua_vanjaram_get_xcp_res_info()
524 if (adev->gmc.num_mem_partitions == 1) in __aqua_vanjaram_get_auto_mode()
527 if (adev->gmc.num_mem_partitions == num_xcc) in __aqua_vanjaram_get_auto_mode()
530 if (adev->gmc.num_mem_partitions == num_xcc / 2) in __aqua_vanjaram_get_auto_mode()
534 if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU)) in __aqua_vanjaram_get_auto_mode()
549 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; in __aqua_vanjaram_is_valid_mode()
551 return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; in __aqua_vanjaram_is_valid_mode()
553 return (adev->gmc.num_mem_partitions == 1 || in __aqua_vanjaram_is_valid_mode()
554 adev->gmc.num_mem_partitions == 3) && in __aqua_vanjaram_is_valid_mode()
558 return (adev->gmc.num_mem_partitions == 1 || in __aqua_vanjaram_is_valid_mode()
[all …]
H A Dmmhub_v2_3.c140 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
157 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_3_init_system_aperture_regs()
158 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_3_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v2_3_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v2_3_init_system_aperture_regs()
228 if (adev->gmc.translate_further) { in mmhub_v2_3_init_cache_regs()
313 !adev->gmc.noretry); in mmhub_v2_3_setup_vmid_config()
[all …]
H A Dmmhub_v1_7.c48 adev->gmc.fb_start = base; in mmhub_v1_7_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_7_get_fb_location()
70 if (adev->gmc.pdb0_bo) in mmhub_v1_7_init_gart_aperture_regs()
71 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in mmhub_v1_7_init_gart_aperture_regs()
80 if (adev->gmc.pdb0_bo) { in mmhub_v1_7_init_gart_aperture_regs()
82 (u32)(adev->gmc.fb_start >> 12)); in mmhub_v1_7_init_gart_aperture_regs()
84 (u32)(adev->gmc.fb_start >> 44)); in mmhub_v1_7_init_gart_aperture_regs()
87 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_7_init_gart_aperture_regs()
89 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_7_init_gart_aperture_regs()
93 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_7_init_gart_aperture_regs()
[all …]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c15 * GFX PLL is the PLL used by DC, GMC and GPU, the structure of the GFX PLL
23 * ---+---> | div_ref | ---> | loopc | --+--> | / div_out_1 | _____/ _____ GMC
36 unsigned div_out_gmc : 7; /* 13 : 7 GMC output clock divider */
45 unsigned sel_out_gmc : 1; /* 41 gmc output clk enable */
82 unsigned int *gmc, in loongson_gfxpll_get_rates() argument
110 if (gmc) in loongson_gfxpll_get_rates()
111 *gmc = gmc_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()
[all …]

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