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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v8_0.c35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
262 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v8_0_init_microcode()
266 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_init_microcode()
295 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
298 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
301 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
304 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
307 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
364 if (!adev->gmc.fw) in gmc_v8_0_polaris_mc_load_microcode()
[all …]
H A Dgmc_v7_0.c40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
160 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v7_0_init_microcode()
164 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v7_0_init_microcode()
185 if (!adev->gmc.fw) in gmc_v7_0_mc_load_microcode()
188 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v7_0_mc_load_microcode()
191 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v7_0_mc_load_microcode()
194 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
197 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
294 adev->gmc.vram_start >> 12); in gmc_v7_0_mc_program()
[all …]
H A Dgmc_v12_0.c159 adev->gmc.vm_fault.num_types = 1; in gmc_v12_0_set_irq_funcs()
160 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; in gmc_v12_0_set_irq_funcs()
163 adev->gmc.ecc_irq.num_types = 1; in gmc_v12_0_set_irq_funcs()
164 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; in gmc_v12_0_set_irq_funcs()
213 spin_lock(&adev->gmc.invalidate_lock); in gmc_v12_0_flush_vm_hub()
272 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v12_0_flush_vm_hub()
477 adev->gmc.vram_start; in gmc_v12_0_get_vm_pde()
480 if (!adev->gmc.translate_further) in gmc_v12_0_get_vm_pde()
573 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; in gmc_v12_0_set_gmc_funcs()
626 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v12_0_early_init()
[all …]
H A Damdgpu_xgmi.c442 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); in amdgpu_xgmi_show_device_id()
453 return sysfs_emit(buf, "%u\n", adev->gmc.xgmi.physical_node_id); in amdgpu_xgmi_show_physical_id()
502 if (top->nodes[i].node_id == adev->gmc.xgmi.node_id) { in amdgpu_xgmi_show_connected_port_num()
670 if (!adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
681 if (hive->hive_id == adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
733 hive->hive_id = adev->gmc.xgmi.hive_id; in amdgpu_get_xgmi_hive()
805 request_adev->gmc.xgmi.node_id, in amdgpu_xgmi_set_pstate()
806 request_adev->gmc.xgmi.hive_id, ret); in amdgpu_xgmi_set_pstate()
837 adev->gmc.xgmi.node_id, in amdgpu_xgmi_update_topology()
838 adev->gmc.xgmi.hive_id, ret); in amdgpu_xgmi_update_topology()
[all …]
H A Dgfxhub_v1_1.c88 if (max_region || adev->gmc.xgmi.connected_to_cpu) { in gfxhub_v1_1_get_xgmi_info()
89 adev->gmc.xgmi.num_physical_nodes = max_region + 1; in gfxhub_v1_1_get_xgmi_info()
91 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) in gfxhub_v1_1_get_xgmi_info()
95 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
99 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
104 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) in gfxhub_v1_1_get_xgmi_info()
107 adev->gmc.xgmi.node_segment_size = seg_size; in gfxhub_v1_1_get_xgmi_info()
H A Dmmhub_v1_0.c48 adev->gmc.fb_start = base; in mmhub_v1_0_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_0_get_fb_location()
75 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v1_0_init_system_aperture_regs()
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v1_0_init_system_aperture_regs()
97 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v1_0_init_system_aperture_regs()
109 max((adev->gmc.fb_end >> 18) + 0x1, in mmhub_v1_0_init_system_aperture_regs()
[all …]
H A Dgfxhub_v12_0.c148 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
153 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
155 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
164 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v12_0_init_system_aperture_regs()
165 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v12_0_init_system_aperture_regs()
169 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v12_0_init_system_aperture_regs()
171 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v12_0_init_system_aperture_regs()
174 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start in gfxhub_v12_0_init_system_aperture_regs()
242 if (adev->gmc.translate_further) { in gfxhub_v12_0_init_cache_regs()
[all …]
H A Dgfxhub_v11_5_0.c145 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
152 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
160 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
165 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v11_5_0_init_system_aperture_regs()
168 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v11_5_0_init_system_aperture_regs()
237 if (adev->gmc.translate_further) { in gfxhub_v11_5_0_init_cache_regs()
364 adev->gmc.vram_start >> 24); in gfxhub_v11_5_0_gart_enable()
[all …]
H A Dgfxhub_v3_0.c140 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_init_system_aperture_regs()
157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
234 if (adev->gmc.translate_further) { in gfxhub_v3_0_init_cache_regs()
361 adev->gmc.vram_start >> 24); in gfxhub_v3_0_gart_enable()
[all …]
H A Dgfxhub_v2_0.c141 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
143 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_0_init_system_aperture_regs()
159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_0_init_system_aperture_regs()
163 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
165 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
233 if (adev->gmc.translate_further) { in gfxhub_v2_0_init_cache_regs()
314 !adev->gmc.noretry); in gfxhub_v2_0_setup_vmid_config()
H A Dmmhub_v2_3.c140 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
157 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_3_init_system_aperture_regs()
158 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_3_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v2_3_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v2_3_init_system_aperture_regs()
228 if (adev->gmc.translate_further) { in mmhub_v2_3_init_cache_regs()
313 !adev->gmc.noretry); in mmhub_v2_3_setup_vmid_config()
[all …]
H A Dgfxhub_v3_0_3.c143 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
162 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
167 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_3_init_system_aperture_regs()
169 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v3_0_3_init_system_aperture_regs()
239 if (adev->gmc.translate_further) { in gfxhub_v3_0_3_init_cache_regs()
H A Dmmhub_v3_3.c259 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_3_init_gart_aperture_regs()
261 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_3_init_gart_aperture_regs()
264 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_3_init_gart_aperture_regs()
266 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_3_init_gart_aperture_regs()
276 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_3_init_system_aperture_regs()
277 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_3_init_system_aperture_regs()
286 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_3_init_system_aperture_regs()
288 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_3_init_system_aperture_regs()
353 if (adev->gmc.translate_further) { in mmhub_v3_3_init_cache_regs()
482 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_3_init_saw_regs()
[all …]
H A Damdgpu_amdkfd.c229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; in amdgpu_amdkfd_device_init()
240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; in amdgpu_amdkfd_device_fini_sw()
483 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) in amdgpu_amdkfd_get_local_mem_info()
493 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
494 mem_info->local_mem_size_private = adev->gmc.real_vram_size - in amdgpu_amdkfd_get_local_mem_info()
495 adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
497 mem_info->vram_width = adev->gmc.vram_width; in amdgpu_amdkfd_get_local_mem_info()
500 &adev->gmc.aper_base, in amdgpu_amdkfd_get_local_mem_info()
790 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { in amdgpu_amdkfd_xcp_memory_size()
791 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { in amdgpu_amdkfd_xcp_memory_size()
[all …]
H A Dmmhub_v4_1_0.c149 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v4_1_0_init_gart_aperture_regs()
151 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v4_1_0_init_gart_aperture_regs()
154 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v4_1_0_init_gart_aperture_regs()
156 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v4_1_0_init_gart_aperture_regs()
174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v4_1_0_init_system_aperture_regs()
175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v4_1_0_init_system_aperture_regs()
179 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v4_1_0_init_system_aperture_regs()
181 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v4_1_0_init_system_aperture_regs()
184 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start + in mmhub_v4_1_0_init_system_aperture_regs()
253 if (adev->gmc.translate_further) { in mmhub_v4_1_0_init_cache_regs()
H A Damdgpu_vram_mgr.c107 return sysfs_emit(buf, "%llu\n", adev->gmc.real_vram_size); in amdgpu_mem_info_vram_total_show()
124 return sysfs_emit(buf, "%llu\n", adev->gmc.visible_vram_size); in amdgpu_mem_info_vis_vram_total_show()
180 switch (adev->gmc.vram_vendor) { in amdgpu_mem_info_vram_vendor()
234 !adev->gmc.vram_vendor) in amdgpu_vram_attrs_is_visible()
262 if (start >= adev->gmc.visible_vram_size) in amdgpu_vram_mgr_vis_size()
265 return (end > adev->gmc.visible_vram_size ? in amdgpu_vram_mgr_vis_size()
266 adev->gmc.visible_vram_size : end) - start; in amdgpu_vram_mgr_vis_size()
285 if (amdgpu_gmc_vram_full_visible(&adev->gmc)) in amdgpu_vram_mgr_bo_visible_size()
288 if (res->start >= adev->gmc.visible_vram_size >> PAGE_SHIFT) in amdgpu_vram_mgr_bo_visible_size()
464 max_bytes = adev->gmc.mc_vram_size; in amdgpu_vram_mgr_new()
[all …]
H A Dmmhub_v3_0_2.c150 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
152 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
155 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
157 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
168 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
178 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_2_init_system_aperture_regs()
180 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_2_init_system_aperture_regs()
252 if (adev->gmc.translate_further) { in mmhub_v3_0_2_init_cache_regs()
H A Dmmhub_v3_0_1.c166 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_1_init_gart_aperture_regs()
168 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_1_init_gart_aperture_regs()
171 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_1_init_gart_aperture_regs()
173 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_1_init_gart_aperture_regs()
183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_1_init_system_aperture_regs()
184 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_1_init_system_aperture_regs()
193 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_1_init_system_aperture_regs()
195 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_1_init_system_aperture_regs()
260 if (adev->gmc.translate_further) { in mmhub_v3_0_1_init_cache_regs()
H A Dmmhub_v2_0.c208 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v2_0_init_gart_aperture_regs()
210 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v2_0_init_gart_aperture_regs()
213 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v2_0_init_gart_aperture_regs()
215 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v2_0_init_gart_aperture_regs()
226 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_0_init_system_aperture_regs()
227 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_0_init_system_aperture_regs()
231 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v2_0_init_system_aperture_regs()
233 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v2_0_init_system_aperture_regs()
304 if (adev->gmc.translate_further) { in mmhub_v2_0_init_cache_regs()
395 !adev->gmc.noretry); in mmhub_v2_0_setup_vmid_config()
H A Daqua_vanjaram.c294 (adev->gmc.supported_nps_modes & nps_modes); in aqua_vanjaram_get_xcp_res_info()
321 if (adev->gmc.num_mem_partitions == 1) in __aqua_vanjaram_get_auto_mode()
324 if (adev->gmc.num_mem_partitions == num_xcc) in __aqua_vanjaram_get_auto_mode()
327 if (adev->gmc.num_mem_partitions == num_xcc / 2) in __aqua_vanjaram_get_auto_mode()
331 if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU)) in __aqua_vanjaram_get_auto_mode()
346 nps_mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); in __aqua_vanjaram_is_valid_mode()
400 adev->gmc.num_mem_partitions); in aqua_vanjaram_switch_partition_mode()
406 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); in aqua_vanjaram_switch_partition_mode()
466 if (adev->gmc.gmc_funcs->query_mem_partition_mode) in aqua_vanjaram_get_xcp_mem_id()
467 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); in aqua_vanjaram_get_xcp_mem_id()
[all …]
H A Dmmhub_v3_0.c157 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_init_gart_aperture_regs()
159 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_init_gart_aperture_regs()
162 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_init_gart_aperture_regs()
164 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_init_gart_aperture_regs()
182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_init_system_aperture_regs()
183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_init_system_aperture_regs()
187 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_init_system_aperture_regs()
189 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_init_system_aperture_regs()
260 if (adev->gmc.translate_further) { in mmhub_v3_0_init_cache_regs()
H A Dumc_v8_10.h37 (adev)->gmc.num_umc - hweight32((adev)->gmc.m_half_use) * 2)
H A Damdgpu_device.c510 if (!adev->gmc.noretry && !amdgpu_passthrough(adev)) in amdgpu_device_detect_runtime_pm_mode()
624 last = min(pos + size, adev->gmc.visible_vram_size); in amdgpu_device_aper_access()
1673 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); in amdgpu_device_resize_fb_bar()
1704 if (adev->gmc.real_vram_size && in amdgpu_device_resize_fb_bar()
1705 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) in amdgpu_device_resize_fb_bar()
2460 [AMD_IP_BLOCK_TYPE_GMC] = "gmc",
2920 if (adev->gmc.xgmi.supported) in amdgpu_device_ip_early_init()
3146 /* need to do common hw init early so everything is set up for gmc */ in amdgpu_device_ip_init()
3155 /* need to do gmc hw init early so we can allocate gpu mem */ in amdgpu_device_ip_init()
3181 /* right after GMC hw init, we create CSA */ in amdgpu_device_ip_init()
[all …]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c15 * GFX PLL is the PLL used by DC, GMC and GPU, the structure of the GFX PLL
23 * ---+---> | div_ref | ---> | loopc | --+--> | / div_out_1 | _____/ _____ GMC
36 unsigned div_out_gmc : 7; /* 13 : 7 GMC output clock divider */
45 unsigned sel_out_gmc : 1; /* 41 gmc output clk enable */
82 unsigned int *gmc, in loongson_gfxpll_get_rates() argument
110 if (gmc) in loongson_gfxpll_get_rates()
111 *gmc = gmc_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_common.h37 #include "gmc/gmc_8_1_d.h"
38 #include "gmc/gmc_8_1_sh_mask.h"

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