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/linux/Documentation/devicetree/bindings/net/
H A Dthead,th1520-gmac.yaml4 $id: http://devicetree.org/schemas/net/thead,th1520-gmac.yaml#
7 title: T-HEAD TH1520 GMAC Ethernet controller
13 The TH1520 GMAC is described in the TH1520 Peripheral Interface User Manual
26 The GMAC Registers consists of two parts
29 - AHB registers are use to configure GMAC core (DesignWare Core part).
30 GMAC core register consists of DMA registers and GMAC registers.
37 - thead,th1520-gmac
48 - thead,th1520-gmac
53 - description: DesignWare GMAC IP core registers
54 - description: GMAC APB registers
[all …]
H A Dhisilicon-hix5hd2-gmac.txt1 Hisilicon hix5hd2 gmac controller
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
43 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
H A Dallwinner,sun7i-a20-gmac.yaml4 $id: http://devicetree.org/schemas/net/allwinner,sun7i-a20-gmac.yaml#
7 title: Allwinner A20 GMAC
18 const: allwinner,sun7i-a20-gmac
31 - description: GMAC main clock
56 gmac: ethernet@1c50000 {
57 compatible = "allwinner,sun7i-a20-gmac";
H A Dmediatek-dwmac.yaml21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
35 - mediatek,mt2712-gmac
39 - mediatek,mt8195-gmac
43 - mediatek,mt8188-gmac
44 - const: mediatek,mt8195-gmac
161 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
H A Dloongson,ls1b-gmac.yaml4 $id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml#
17 - Dual 10/100/1000Mbps GMAC controllers
30 - loongson,ls1b-gmac
38 - loongson,ls1b-gmac
89 compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";
H A Dipq806x-dwmac.txt8 - compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
20 gmac: ethernet@37000000 {
22 compatible = "qcom,ipq806x-gmac";
H A Danarion-gmac.txt7 - compatible: Should be "adaptrum,anarion-gmac", "snps,dwmac"
14 compatible = "adaptrum,anarion-gmac", "snps,dwmac";
/linux/drivers/clk/sunxi/
H A Dclk-a20-gmac.c29 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
34 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
35 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
39 * The external 125 MHz reference is optional, i.e. GMAC can use its
40 * internal TX clock just fine. The A31 GMAC clock module does not have
43 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
44 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
47 * Only the GMAC should use this clock. Altering the clock so that it doesn't
48 * match the GMAC's operation parameters will result in the GMAC not being
49 * able to send traffic out. The GMAC driver should set the clock rate and
[all …]
/linux/drivers/net/ethernet/cortina/
H A Dgemini.h2 /* Register definitions for Gemini GMAC Ethernet device driver
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
91 /* GMAC 0/1 DMA/TOE register */
145 /* GMAC Hash/Rx/Tx AHB Weighting register */
148 /* TOE GMAC 0/1 register */
332 /* GMAC DMA Control Register
366 /* GMAC Tx Weighting Control Register 0
386 /* GMAC Tx Weighting Control Register 1
410 /* GMAC DMA Tx Description Word 0 Register
434 /* GMAC DMA Tx Description Word 1 Register
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun7i-a20-gmac-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml#
7 title: Allwinner A20 GMAC TX Clock
18 const: allwinner,sun7i-a20-gmac-clk
45 compatible = "allwinner,sun7i-a20-gmac-clk";
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun8i-a83t.c185 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */
190 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */
195 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */
200 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */
205 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */
210 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */
215 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */
220 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */
225 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */
230 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */
[all …]
H A Dpinctrl-sun9i-a80.c24 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
30 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
36 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
42 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
48 SUNXI_FUNCTION(0x2, "gmac"), /* RXCK */
54 SUNXI_FUNCTION(0x2, "gmac"), /* RXCTL */
60 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
66 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
72 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
78 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5-nanopi-neo-plus2.dts40 reg_gmac_3v3: gmac-3v3 {
42 regulator-name = "gmac-3v3";
51 reg_gmac_2v5: gmac-2v5 {
52 /* 2V5 supply for GMAC PHY IO */
54 regulator-name = "gmac-2v5";
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-rk.c1709 static void rk_gmac_powerdown(struct rk_priv_data *gmac) in rk_gmac_powerdown() argument
1711 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown) in rk_gmac_powerdown()
1712 gmac->ops->integrated_phy_powerdown(gmac); in rk_gmac_powerdown()
1714 pm_runtime_put_sync(gmac->dev); in rk_gmac_powerdown()
1716 phy_power_on(gmac, false); in rk_gmac_powerdown()
1717 gmac_clk_enable(gmac, false); in rk_gmac_powerdown()
1803 * then make sure we fallback to gmac. in rk_gmac_probe()
1830 { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
1831 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1832 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-ficus.dts17 ethernet0 = &gmac;
24 clkin_gmac: external-gmac-clock {
79 &gmac {
100 gmac {
H A Drk3399-khadas-edge-v.dts15 ethernet0 = &gmac;
19 &gmac {
H A Drk3399-khadas-edge-captain.dts15 ethernet0 = &gmac;
19 &gmac {
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dgmac.h4 * File: gmac.h *
123 struct gmac { struct
129 extern const struct gmac t1_pm3393_ops; argument
130 extern const struct gmac t1_vsc7326_ops;
/linux/drivers/net/ethernet/marvell/
H A Dsky2.h74 P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */
75 P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */
829 /* Receive GMAC FIFO (YUKON and Yukon-2) */
831 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
832 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
833 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
834 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
835 RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */
836 RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */
841 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
[all …]
H A Dskge.h510 SK_MAC_GMAC = 1, /* Marvell GMAC */
664 /* Receive GMAC FIFO (YUKON) */
666 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
667 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
668 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
669 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
670 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
671 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
672 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
673 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
[all …]
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst27 Currently, this network device driver is for all STi embedded MAC/GMAC
46 | Ethernet MAC Universal | N/A | 3.73a | GMAC |
227 GMAC, GMAC4/5 and XGMAC core.
249 GMAC Synopsys(R) chips older than the 3.50. At probe time the driver will
270 Jumbo frames are supported and tested for the GMAC. The GSO has been also
276 TSO (TCP Segmentation Offload) feature is supported by GMAC > 4.x and XGMAC
286 and provide SKB packet to stmmac as it is. The GMAC IP will have to perform
319 Timestamps, new GMAC cores support the advanced timestamp features.
325 New GMAC devices provide own way to manage RGMII/SGMII. This information is
372 7) HW uses the GMAC core::
[all …]
/linux/net/mac80211/
H A Daes_gmac.c3 * AES-GMAC for IEEE 802.11 BIP-GMAC-128 and BIP-GMAC-256
/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-haoyu-marsboard.dts63 &gmac {
117 gmac_txerr: gmac-txerr-pin {
119 function = "gmac";
H A Dsun7i-a20-lamobo-r1.dts84 reg_gmac_3v3: gmac-3v3 {
86 regulator-name = "gmac-3v3";
120 &gmac {
173 ethernet = <&gmac>;
/linux/arch/riscv/boot/dts/starfive/
H A Djh7100-starfive-visionfive-v1.dts21 &gmac {
33 * responsible for the misbehaviour, not the GMAC.

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