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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
21 - one or more IRS (Interrupt Routing Service)
22 - zero or more ITS (Interrupt Translation Service)
25 - PE-Private Peripheral Interrupts (PPI)
26 - Shared Peripheral Interrupts (SPI)
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H A Darm,gic-v5-iwb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
24 - $ref: /schemas/interrupt-controller.yaml#
28 const: arm,gic-v5-iwb
32 - description: IWB control frame
34 "#address-cells":
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8998-bwmon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8998-bwmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
17 - Measuring the bandwidth between CPUs and Last Level Cache Controller -
19 - Measuring the bandwidth between Last Level Cache Controller and memory
20 (DDR) - called LLCC BWMON.
25 - const: qcom,msm8998-bwmon # BWMON v4
26 - items:
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/linux/Documentation/devicetree/bindings/media/
H A Dsamsung,s5p-mfc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Aakarsh Jain <aakarsh.jain@samsung.com>
20 - enum:
21 - samsung,exynos5433-mfc # Exynos5433
22 - samsung,mfc-v5 # Exynos4
23 - samsung,mfc-v6 # Exynos5
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/linux/drivers/irqchip/
H A Dirq-gic-v5-iwb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved.
15 #include <linux/irqchip/arm-gic-v5.h>
24 return readl_relaxed(iwb_node->iwb_base + reg_offset); in iwb_readl_relaxed()
30 writel_relaxed(val, iwb_node->iwb_base + reg_offset); in iwb_writel_relaxed()
35 return gicv5_wait_for_op_atomic(iwb_node->iwb_base, GICV5_IWB_WENABLE_STATUSR, in gicv5_iwb_wait_for_wenabler()
46 if (n >= iwb_node->nr_regs) { in __gicv5_iwb_set_wire_enable()
48 return -EINVAL; in __gicv5_iwb_set_wire_enable()
81 gicv5_iwb_disable_wire(iwb_node, d->hwirq); in gicv5_iwb_irq_disable()
89 gicv5_iwb_enable_wire(iwb_node, d->hwirq); in gicv5_iwb_irq_enable()
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H A Dirq-gic-v5-irs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved.
14 #include <linux/irqchip/arm-gic-v5.h>
17 * Hardcoded ID_BITS limit for systems supporting only a 1-level IST
18 * table. Systems supporting only a 1-level IST table aren't expected
31 return readl_relaxed(irs_data->irs_base + reg_offset); in irs_readl_relaxed()
37 writel_relaxed(val, irs_data->irs_base + reg_offset); in irs_writel_relaxed()
43 return readq_relaxed(irs_data->irs_base + reg_offset); in irs_readq_relaxed()
49 writeq_relaxed(val, irs_data->irs_base + reg_offset); in irs_writeq_relaxed()
53 * The polling wait (in gicv5_wait_for_op_s_atomic()) on a GIC register
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H A Dirq-gic-v5-its.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved.
19 #include <linux/irqchip/arm-gic-v5.h>
20 #include <linux/irqchip/irq-msi-lib.h>
22 #include "irq-gic-its-msi-parent.h"
47 return readl_relaxed(its_node->its_base + reg_offset); in its_readl_relaxed()
53 writel_relaxed(val, its_node->its_base + reg_offset); in its_writel_relaxed()
59 writeq_relaxed(val, its_node->its_base + reg_offset); in its_writeq_relaxed()
67 if (its->flags & ITS_FLAGS_NON_COHERENT) in gicv5_its_dcache_clean()
81 FIELD_GET(GICV5_ITS_DT_CFGR_##f, (its)->devtab_cfgr.cfgr)
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H A Dirq-gic-its-msi-parent.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
11 #include "irq-gic-its-msi-parent.h"
12 #include <linux/irqchip/irq-msi-lib.h>
27 ret = of_property_match_string(msi_node, "reg-names", "ns-translate"); in its_translate_frame_address()
68 return -EINVAL; in its_pci_msi_prepare()
79 if (alias_dev->subordinate) in its_pci_msi_prepare()
80 pci_walk_bus(alias_dev->subordinate, in its_pci_msi_prepare()
82 info->flags |= MSI_ALLOC_FLAGS_PROXY_DEVICE; in its_pci_msi_prepare()
86 info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain->parent, pdev); in its_pci_msi_prepare()
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/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-c3-c308l-aw419.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "amlogic-c3.dtsi"
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
27 reserved-memory {
28 #address-cells = <2>;
29 #size-cells = <2>;
34 compatible = "shared-dma-pool";
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H A Damlogic-c3-c302x-aw409.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "amlogic-c3.dtsi"
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
27 reserved-memory {
28 #address-cells = <2>;
29 #size-cells = <2>;
34 compatible = "shared-dma-pool";
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
16 interrupt-parent = <&intc>;
[all …]
H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
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H A Dqdu1000.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
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H A Dsdm630.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
9 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
10 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/interconnect/qcom,sdm660.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/gpio/gpio.h>
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H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
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H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
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