Searched +full:gic +full:- +full:v5 +full:- +full:irs (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Lorenzo Pieralisi <lpieralisi@kernel.org>11 - Marc Zyngier <maz@kernel.org>21 - one or more IRS (Interrupt Routing Service)22 - zero or more ITS (Interrupt Translation Service)25 - PE-Private Peripheral Interrupts (PPI)26 - Shared Peripheral Interrupts (SPI)[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved.6 #define pr_fmt(fmt) "GICv5 IRS: " fmt14 #include <linux/irqchip/arm-gic-v5.h>17 * Hardcoded ID_BITS limit for systems supporting only a 1-level IST18 * table. Systems supporting only a 1-level IST table aren't expected31 return readl_relaxed(irs_data->irs_base + reg_offset); in irs_readl_relaxed()37 writel_relaxed(val, irs_data->irs_base + reg_offset); in irs_writel_relaxed()43 return readq_relaxed(irs_data->irs_base + reg_offset); in irs_readq_relaxed()49 writeq_relaxed(val, irs_data->irs_base + reg_offset); in irs_writeq_relaxed()[all …]