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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
[all …]
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
38 For GICv3 and GIC ITS bindings, see:
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
[all …]
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dfoundation-v8-gicv3.dtsi8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
10 #interrupt-cells = <3>;
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-controller;
22 its label
[all...]
H A Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/cavium/
H A Dthunder2-99xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2013-2016 Broadcom
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
28 enable-method = "psci";
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H A Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
63 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Delba.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include "dt-bindings/interrupt-controller/arm-gic.h"
11 compatible = "amd,pensando-elba";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 dma-coherent;
19 compatible = "fixed-clock";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Darm,smmu-v3-pmcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <robin.murphy@arm.com>
20 pattern: "^pmu@[0-9a-f]*"
23 - items:
24 - const: arm,mmu-600-pmcg
25 - const: arm,smmu-v3-pmcg
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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/freebsd/sys/contrib/device-tree/src/arm64/amazon/
H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 model = "Amazon's Annapurna Labs Alpine v3";
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
[all …]
H A Dalpine-v2.dtsi2 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 interrupt-parent = <&gic>;
43 #address-cells = <2>;
44 #size-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/al/
H A Dalpine-v2.dtsi2 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
[all …]
/freebsd/sys/arm64/arm64/
H A Dgic_v3_fdt.c1 /*-
78 DEFINE_CLASS_1(gic, gic_v3_fdt_driver, gic_v3_fdt_methods,
101 if (!ofw_bus_is_compatible(dev, "arm,gic-v3")) in gic_v3_fdt_probe()
119 sc->dev = dev; in gic_v3_fdt_attach()
120 sc->gic_bus = GIC_BUS_FDT; in gic_v3_fdt_attach()
123 * Recover number of the Re-Distributor regions. in gic_v3_fdt_attach()
125 if (OF_getencprop(ofw_bus_get_node(dev), "#redistributor-regions", in gic_v3_fdt_attach()
127 sc->gic_redists.nregions = 1; in gic_v3_fdt_attach()
129 sc->gic_redists.nregions = redist_regions; in gic_v3_fdt_attach()
132 ret = OF_getencprop_alloc_multi(ofw_bus_get_node(dev), "mbi-ranges", in gic_v3_fdt_attach()
[all …]
H A Dgic_v3_reg.h1 /*-
34 * supported by GIC (including SGIs, PPIs and SPIs)
50 * Registers (v2/v3)
67 * Registers (v3)
145 * 0x0 - Device-nGnRnE
146 * 0x1 - Normal Inner Non-cacheable
147 * 0x2 - Normal Inner Read-allocate, Write-through
148 * 0x3 - Normal Inner Read-allocate, Write-back
149 * 0x4 - Normal Inner Write-allocate, Write-through
150 * 0x5 - Normal Inner Write-allocate, Write-back
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
16 * * Neither the name of Broadcom nor the names of its
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dqcom,wcnss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,wcnss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
21 - items:
22 - enum:
23 - qcom,pronto-v1-pil
24 - qcom,pronto-v2-pil
25 - qcom,pronto-v3-pil
[all …]

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