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Searched +full:gfx +full:- +full:mem (Results 1 – 25 of 37) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_kms.c59 if (gpu_instance->adev == adev) { in amdgpu_unregister_gpu_instance()
61 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; in amdgpu_unregister_gpu_instance()
62 mgpu_info.num_gpu--; in amdgpu_unregister_gpu_instance()
63 if (adev->flags & AMD_IS_APU) in amdgpu_unregister_gpu_instance()
64 mgpu_info.num_apu--; in amdgpu_unregister_gpu_instance()
66 mgpu_info.num_dgpu--; in amdgpu_unregister_gpu_instance()
75 * amdgpu_driver_unload_kms - Main unload function for KMS.
91 if (adev->rmmio == NULL) in amdgpu_driver_unload_kms()
114 gpu_instance->adev = adev; in amdgpu_register_gpu_instance()
115 gpu_instance->mgpu_fan_enabled = 0; in amdgpu_register_gpu_instance()
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H A Damdgpu_amdkfd_gpuvm.c1 // SPDX-License-Identifier: MIT
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
23 #include <linux/dma-buf.h>
73 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
78 struct kgd_mem *mem) in kfd_mem_is_attached() argument
82 list_for_each_entry(entry, &mem->attachments, list) in kfd_mem_is_attached()
83 if (entry->bo_va->base.vm == avm) in kfd_mem_is_attached()
90 * reuse_dmamap() - Check whether adev can share the original
104 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) || in reuse_dmamap()
105 (adev->dev->iommu_group == bo_adev->dev->iommu_group); in reuse_dmamap()
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H A Damdgpu_vm.c29 #include <linux/dma-fence-array.h>
32 #include <linux/dma-buf.h>
69 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
90 #define START(node) ((node)->start)
91 #define LAST(node) ((node)->last)
100 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
116 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
131 * amdgpu_vm_assert_locked - check if VM is correctly locked
138 dma_resv_assert_held(vm->root.bo->tbo.base.resv); in amdgpu_vm_assert_locked()
142 * amdgpu_vm_bo_evicted - vm_bo is evicted
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H A Dsdma_v4_4_2.c121 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); in sdma_v4_4_2_get_reg_offset()
136 return -EINVAL; in sdma_v4_4_2_seq_to_irq_id()
148 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
153 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
158 return -EINVAL; in sdma_v4_4_2_irq_id_to_seq()
168 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
185 * sdma_v4_4_2_init_microcode - load ucode images from disk
197 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_init_microcode()
214 * sdma_v4_4_2_ring_get_rptr - get the current read pointer
225 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); in sdma_v4_4_2_ring_get_rptr()
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H A Damdgpu_device.c37 #include <linux/pci-p2pdma.h>
38 #include <linux/apple-gmux.h>
87 #include <asm/intel-family.h>
102 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
153 #define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMD_IP_BLOCK_TYPE_NUM - 1, 0)
187 return (adev->init_lvl->hwini_ip_block_mask & (1U << block)) != 0; in amdgpu_ip_member_of_hwini()
195 adev->init_lvl = &amdgpu_init_minimal_xgmi; in amdgpu_set_init_level()
198 adev->init_lvl = &amdgpu_init_recovery; in amdgpu_set_init_level()
203 adev->init_lvl = &amdgpu_init_default; in amdgpu_set_init_level()
239 ret = sysfs_create_file(&adev->dev->kobj, in amdgpu_device_attr_sysfs_init()
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H A Damdgpu_vm.h55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
89 /* Flag combination to set no-retry with TF disabled */
93 /* Flag combination to set no-retry with TF enabled */
134 /* PDE Block Fragment Size for gfx v12 */
138 /* PDE is handled as PTE for gfx v12 */
169 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \
171 - AMDGPU_VA_RESERVED_CSA_SIZE)
174 - AMDGPU_VA_RESERVED_SEQ64_SIZE)
177 - AMDGPU_VA_RESERVED_TRAP_SIZE)
188 * PDB2->PDB1->PDB0->PTB
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H A Dsdma_v5_2.c125 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_2_get_reg_offset()
130 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_2_get_reg_offset()
134 base = adev->reg_offset[GC_HWIP][0][2]; in sdma_v5_2_get_reg_offset()
153 ret = ring->wptr & ring->buf_mask; in sdma_v5_2_ring_init_cond_exec()
161 * sdma_v5_2_ring_get_rptr - get the current read pointer
172 rptr = (u64 *)ring->rptr_cpu_addr; in sdma_v5_2_ring_get_rptr()
179 * sdma_v5_2_ring_get_wptr - get the current write pointer
187 struct amdgpu_device *adev = ring->adev; in sdma_v5_2_ring_get_wptr()
190 if (ring->use_doorbell) { in sdma_v5_2_ring_get_wptr()
192 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v5_2_ring_get_wptr()
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H A Dsdma_v5_0.c224 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_0_get_reg_offset()
228 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_0_get_reg_offset()
279 * sdma_v5_0_init_microcode - load ucode images from disk
294 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
313 ret = ring->wptr & ring->buf_mask; in sdma_v5_0_ring_init_cond_exec()
321 * sdma_v5_0_ring_get_rptr - get the current read pointer
332 rptr = (u64 *)ring->rptr_cpu_addr; in sdma_v5_0_ring_get_rptr()
339 * sdma_v5_0_ring_get_wptr - get the current write pointer
347 struct amdgpu_device *adev = ring->adev; in sdma_v5_0_ring_get_wptr()
350 if (ring->use_doorbell) { in sdma_v5_0_ring_get_wptr()
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/linux/arch/mips/include/asm/sgi/
H A Dmc.h22 #define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
32 #define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
33 #define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
34 #define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
35 #define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
36 #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
64 #define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
65 #define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
75 #define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
76 #define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
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/linux/drivers/usb/misc/sisusbvga/
H A Dsisusb.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
3 * sisusb - usb kernel driver for Net2280/SiS315 based USB2VGA dongles
83 p->header = cpu_to_le16(p->header); \
84 p->address = cpu_to_le32(p->address); \
85 p->data = cpu_to_le32(p->data); \
93 struct sisusb_urb_context { /* urb->context for outbound bulk URBs */
140 #define SISUSB_EP_GFX_IN 0x0e /* gfx std packet out(0e)/in(8e) */
143 #define SISUSB_EP_GFX_BULK_OUT 0x01 /* gfx mem bulk out/in */
146 #define SISUSB_EP_GFX_LBULK_OUT 0x03 /* gfx large mem bulk out */
148 #define SISUSB_EP_UNKNOWN_04 0x04 /* ? 4 is "OUT" ? - unused */
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/linux/include/uapi/drm/
H A Damdgpu_drm.h1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
90 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
97 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
178 /* Flag that BO should be coherent across devices when using device-leve
1517 struct drm_amdgpu_info_uq_fw_areas_gfx gfx; global() member
1597 struct drm_amdgpu_info_uq_metadata_gfx gfx; global() member
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_topology.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
46 /* topology_device_list - Master list of all topology devices */
60 if (top_dev->proximity_domain == proximity_domain) { in kfd_topology_device_by_proximity_domain_no_lock()
90 if (top_dev->gpu_id == gpu_id) { in kfd_topology_device_by_id()
108 return top_dev->gpu; in kfd_device_by_id()
114 struct kfd_mem_properties *mem; in kfd_release_topology_device() local
120 list_del(&dev->list); in kfd_release_topology_device()
122 while (dev->mem_props.next != &dev->mem_props) { in kfd_release_topology_device()
123 mem = container_of(dev->mem_props.next, in kfd_release_topology_device()
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H A Dcwsr_trap_handler_gfx8.asm2 * Copyright 2015-2017 Advanced Micro Devices, Inc.
24 * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex
103 …buf_rsrc2 //shared with s_save_buf_rsrc2 (conflict: should not use mem access with s_save_…
170 // ********* Handle non-CWSR traps *******************
191 // ********* End handling of non-CWSR traps *******************
226 …could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for …
237 …s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_S…
240 …s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTY…
246 /* global mem offset */
247 … 0x0 //mem offset initial valu…
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H A Dkfd_process_queue_manager.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { in get_queue_by_qid()
39 if ((pqn->q && pqn->q->properties.queue_id == qid) || in get_queue_by_qid()
40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) in get_queue_by_qid()
51 return -EINVAL; in assign_queue_slot_by_qid()
53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { in assign_queue_slot_by_qid()
55 return -ENOSPC; in assign_queue_slot_by_qid()
66 found = find_first_zero_bit(pqm->queue_slot_bitmap, in find_available_queue_slot()
73 pqm->process->lead_thread->pid); in find_available_queue_slot()
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H A Dcwsr_trap_handler_gfx9.asm26 * cpp -DASIC_FAMILY=CHIP_VEGAM cwsr_trap_handler_gfx9.asm -P -o gfx9.sp3
27 * sp3 gfx9.sp3 -hex gfx9.hex
30 * cpp -DASIC_FAMILY=CHIP_ARCTURUS cwsr_trap_handler_gfx9.asm -P -o arcturus.sp3
31 * sp3 arcturus.sp3 -hex arcturus.hex
34 * cpp -DASIC_FAMILY=CHIP_ALDEBARAN cwsr_trap_handler_gfx9.asm -P -o aldebaran.sp3
35 * sp3 aldebaran.sp3 -hex aldebaran.hex
38 * cpp -DASIC_FAMILY=GC_9_4_3 cwsr_trap_handler_gfx9.asm -P -o gc_9_4_3.sp3
39 * sp3 gc_9_4_3.sp3 -hex gc_9_4_3.hex
42 * cpp -DASIC_FAMILY=GC_9_5_0 cwsr_trap_handler_gfx9.asm -P -o gc_9_5_0.sp3
43 * sp3 gc_9_5_0.sp3 -hex gc_9_5_0.hex
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/linux/drivers/video/fbdev/
H A Dsstfb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
5 * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
16 * (enable driver on big-endian machines (hppa), ioctl fixes)
26 * add /sys/class/graphics/fbX/vgapass sysfs-interface
34 * 0x000000 - 0x3fffff : registers (4MB)
35 * 0x400000 - 0x7fffff : linear frame buffer (4MB)
36 * 0x800000 - 0xffffff : texture memory (8MB)
42 -TODO: at one time or another test that the mode is acceptable by the monitor
43 -ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
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/linux/arch/x86/kernel/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * This file contains the setup_arch() code, which handles the architecture-dependent
12 #include <linux/dma-map-ops.h>
27 #include <linux/usb/xhci-dbgp.h>
52 #include <asm/pci-direct.h>
241 * copy_edd() - Copy the BIOS EDD information
261 size_t mask = align - 1; in extend_brk()
288 _brk_end - _brk_start); in reserve_brk()
328 /* We need to move the initrd down into directly mapped mem */ in relocate_initrd()
337 printk(KERN_INFO "Allocated new RAMDISK: [mem %#010llx-%#010llx]\n", in relocate_initrd()
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/linux/arch/mips/include/asm/sn/
H A Dklconfig.h8 * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
85 /* lboard_t->brd_flags fields */
99 /* klinfo->flags fields */
108 #define IS_CONSOLE_IOC3(i) ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
162 (KL_CONFIG_HDR(_nasid)->ch_board_info)
164 (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
167 (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ? \
168 NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
170 #define KL_CONFIG_MAGIC(_nasid) (KL_CONFIG_HDR(_nasid)->ch_magic)
173 (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
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/linux/include/video/
H A Dvga.h2 * linux/include/video/vga.h -- standard VGA chipset interaction
30 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
36 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */
40 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
41 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
49 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
50 #define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
54 /* EGA-specific registers */
59 #define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
60 #define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
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/linux/drivers/char/agp/
H A Dintel-agp.c14 #include "intel-agp.h"
15 #include <drm/intel/intel-gtt.h>
23 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); in intel_fetch_size()
24 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); in intel_fetch_size()
26 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { in intel_fetch_size()
28 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); in intel_fetch_size()
29 agp_bridge->aperture_size_idx = i; in intel_fetch_size()
42 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); in __intel_8xx_fetch_size()
44 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { in __intel_8xx_fetch_size()
46 agp_bridge->previous_size = in __intel_8xx_fetch_size()
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/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996-xiaomi-common.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 compatible = "gpio-gate-clock";
17 #clock-cells = <0>;
18 enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&divclk1_default>;
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H A Dsdm630.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
9 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
10 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/interconnect/qcom,sdm660.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/gpio/gpio.h>
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H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
11 #include <dt-bindings/gpio/gpio.h>
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/linux/Documentation/arch/m68k/
H A Dkernel-options.rst9 Author: Roman.Hodek@informatik.uni-erlangen.de (Roman Hodek)
11 Update: jds@kom.auc.dk (Jes Sorensen) and faq@linux-m68k.org (Chris Lawrence)
58 ----------
76 /dev/ram: -> 0x0100 (initial ramdisk)
77 /dev/hda: -> 0x0300 (first IDE disk)
78 /dev/hdb: -> 0x0340 (second IDE disk)
79 /dev/sda: -> 0x0800 (first SCSI disk)
80 /dev/sdb: -> 0x0810 (second SCSI disk)
81 /dev/sdc: -> 0x0820 (third SCSI disk)
82 /dev/sdd: -> 0x0830 (forth SCSI disk)
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