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Searched +full:gfx +full:- +full:mem (Results 1 – 25 of 60) sorted by relevance

123

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_kms.c58 if (gpu_instance->adev == adev) { in amdgpu_unregister_gpu_instance()
60 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; in amdgpu_unregister_gpu_instance()
61 mgpu_info.num_gpu--; in amdgpu_unregister_gpu_instance()
62 if (adev->flags & AMD_IS_APU) in amdgpu_unregister_gpu_instance()
63 mgpu_info.num_apu--; in amdgpu_unregister_gpu_instance()
65 mgpu_info.num_dgpu--; in amdgpu_unregister_gpu_instance()
74 * amdgpu_driver_unload_kms - Mai
745 struct drm_amdgpu_memory_info mem; amdgpu_info_ioctl() local
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H A Dgfx_v9_4_2.c198 { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x3F }, /* 63 - accum-offset = 256 */
368 dev_err(adev->dev, "failed to get ib (%d).\n", r); in gfx_v9_4_2_run_shader()
374 ib->ptr[i + (shader_offset / 4)] = shader_ptr[i]; in gfx_v9_4_2_run_shader()
377 ib->length_dw = 0; in gfx_v9_4_2_run_shader()
381 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_4_2_run_shader()
382 ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(init_regs[i]) in gfx_v9_4_2_run_shader()
383 - PACKET3_SET_SH_REG_START; in gfx_v9_4_2_run_shader()
384 ib->ptr[ib->length_dw++] = init_regs[i].reg_value; in gfx_v9_4_2_run_shader()
388 gpu_addr = (ib->gpu_addr + (u64)shader_offset) >> 8; in gfx_v9_4_2_run_shader()
389 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_4_2_run_shader()
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H A Damdgpu_atomfirmware.c49 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_atomfirmware_query_firmware_capability()
59 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, in amdgpu_atomfirmware_query_firmware_capability()
64 (mode_info->atom_context->bios + data_offset); in amdgpu_atomfirmware_query_firmware_capability()
65 fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability); in amdgpu_atomfirmware_query_firmware_capability()
83 fw_cap = adev->mode_info.firmware_flags; in amdgpu_atomfirmware_gpu_virtualization_supported()
94 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, in amdgpu_atomfirmware_scratch_regs_init()
97 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + in amdgpu_atomfirmware_scratch_regs_init()
100 adev->bios_scratch_reg_offset = in amdgpu_atomfirmware_scratch_regs_init()
101 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr); in amdgpu_atomfirmware_scratch_regs_init()
110 start_addr = le32_to_cpu(fw_usage->start_address_in_kb); in amdgpu_atomfirmware_allocate_fb_v2_1()
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H A Damdgpu_amdkfd_gpuvm.c1 // SPDX-License-Identifier: MIT
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
23 #include <linux/dma-buf.h>
73 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
78 struct kgd_mem *mem) in kfd_mem_is_attached() argument
82 list_for_each_entry(entry, &mem->attachments, list) in kfd_mem_is_attached()
83 if (entry->bo_va->base.vm == avm) in kfd_mem_is_attached()
90 * reuse_dmamap() - Check whether adev can share the original
104 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) || in reuse_dmamap()
105 (adev->dev->iommu_group == bo_adev->dev->iommu_group); in reuse_dmamap()
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H A Damdgpu_vm.c29 #include <linux/dma-fence-array.h>
32 #include <linux/dma-buf.h>
69 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
90 #define START(node) ((node)->start)
91 #define LAST(node) ((node)->last)
100 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
116 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
131 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
146 if (vm->pasid == pasid) in amdgpu_vm_set_pasid()
149 if (vm->pasid) { in amdgpu_vm_set_pasid()
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H A Dta_ras_if.h141 enum ta_ras_block block_id; // ras-block. i.e. umc, gfx
143 uint32_t sub_block_index; // mem block. i.e. hbm, sram etc.
H A Damdgpu_mes.c46 struct amdgpu_mes *mes = &adev->mes; in amdgpu_mes_kernel_doorbell_get()
49 offset = adev->doorbell_index.sdma_engine[0]; in amdgpu_mes_kernel_doorbell_get()
53 found = find_next_zero_bit(mes->doorbell_bitmap, mes->num_mes_dbs, offset); in amdgpu_mes_kernel_doorbell_get()
54 if (found >= mes->num_mes_dbs) { in amdgpu_mes_kernel_doorbell_get()
56 return -ENOSPC; in amdgpu_mes_kernel_doorbell_get()
59 set_bit(found, mes->doorbell_bitmap); in amdgpu_mes_kernel_doorbell_get()
62 *doorbell_index = mes->db_start_dw_offset + found * 2; in amdgpu_mes_kernel_doorbell_get()
70 struct amdgpu_mes *mes = &adev->mes; in amdgpu_mes_kernel_doorbell_free()
73 rel_index = (doorbell_index - mes->db_start_dw_offset) / 2; in amdgpu_mes_kernel_doorbell_free()
74 old = test_and_clear_bit(rel_index, mes->doorbell_bitmap); in amdgpu_mes_kernel_doorbell_free()
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H A Damdgpu_discovery.c2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
247 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; in amdgpu_discovery_read_binary_from_sysmem()
249 /* This region is read-only and reserved from system use */ in amdgpu_discovery_read_binary_from_sysmem()
250 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); in amdgpu_discovery_read_binary_from_sysmem()
252 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); in amdgpu_discovery_read_binary_from_sysmem()
257 return -ENOENT; in amdgpu_discovery_read_binary_from_sysmem()
272 * but generally it should be in the 60-100ms range. Normally this starts in amdgpu_discovery_read_binary_from_mem()
290 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; in amdgpu_discovery_read_binary_from_mem()
292 adev->mman.discovery_tmr_size, false); in amdgpu_discovery_read_binary_from_mem()
311 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); in amdgpu_discovery_read_binary_from_file()
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H A Damdgpu_device.c37 #include <linux/pci-p2pdma.h>
38 #include <linux/apple-gmux.h>
87 #include <asm/intel-family.h>
100 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
148 #define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMD_IP_BLOCK_TYPE_NUM - 1, 0)
180 return (adev->init_lvl->hwini_ip_block_mask & (1U << block)) != 0; in amdgpu_ip_member_of_hwini()
188 adev->init_lvl = &amdgpu_init_minimal_xgmi; in amdgpu_set_init_level()
191 adev->init_lvl = &amdgpu_init_recovery; in amdgpu_set_init_level()
196 adev->init_lvl = &amdgpu_init_default; in amdgpu_set_init_level()
258 return -EINVAL; in amdgpu_sysfs_reg_state_get()
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H A Dsdma_v4_4_2.c114 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); in sdma_v4_4_2_get_reg_offset()
129 return -EINVAL; in sdma_v4_4_2_seq_to_irq_id()
141 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
146 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
151 return -EINVAL; in sdma_v4_4_2_irq_id_to_seq()
161 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
178 * sdma_v4_4_2_init_microcode - load ucode images from disk
190 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_init_microcode()
207 * sdma_v4_4_2_ring_get_rptr - get the current read pointer
218 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); in sdma_v4_4_2_ring_get_rptr()
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H A Damdgpu_vm.h55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
89 /* Flag combination to set no-retry with TF disabled */
93 /* Flag combination to set no-retry with TF enabled */
134 /* PDE Block Fragment Size for gfx v12 */
138 /* PDE is handled as PTE for gfx v12 */
169 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \
171 - AMDGPU_VA_RESERVED_CSA_SIZE)
174 - AMDGPU_VA_RESERVED_SEQ64_SIZE)
177 - AMDGPU_VA_RESERVED_TRAP_SIZE)
188 * PDB2->PDB1->PDB0->PTB
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H A Damdgpu_ras.c63 "gfx",
101 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT || in get_ras_block_str()
102 ras_block->block >= ARRAY_SIZE(ras_block_string)) in get_ras_block_str()
105 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) in get_ras_block_str()
106 return ras_mca_block_string[ras_block->sub_block_index]; in get_ras_block_str()
108 return ras_block_string[ras_block->block]; in get_ras_block_str()
154 amdgpu_ras_get_context(adev)->error_query_ready = ready; in amdgpu_ras_set_error_query_ready()
160 return amdgpu_ras_get_context(adev)->error_query_ready; in amdgpu_ras_get_error_query_ready()
171 if ((address >= adev->gmc.mc_vram_size) || in amdgpu_reserve_page_direct()
173 dev_warn(adev->dev, in amdgpu_reserve_page_direct()
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_crat.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2015-2022 Advanced Micro Devices, Inc.
41 * @total_cu_count - Total CUs present in the GPU including ones
1024 dev->node_props.cpu_cores_count = cu->num_cpu_cores; in kfd_populated_cu_info_cpu()
1025 dev->node_props.cpu_core_id_base = cu->processor_id_low; in kfd_populated_cu_info_cpu()
1026 if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT) in kfd_populated_cu_info_cpu()
1027 dev->node_props.capability |= HSA_CAP_ATS_PRESENT; in kfd_populated_cu_info_cpu()
1029 pr_debug("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores, in kfd_populated_cu_info_cpu()
1030 cu->processor_id_low); in kfd_populated_cu_info_cpu()
1036 dev->node_props.simd_id_base = cu->processor_id_low; in kfd_populated_cu_info_gpu()
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H A Dkfd_topology.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
46 /* topology_device_list - Master list of all topology devices */
60 if (top_dev->proximity_domain == proximity_domain) { in kfd_topology_device_by_proximity_domain_no_lock()
90 if (top_dev->gpu_id == gpu_id) { in kfd_topology_device_by_id()
108 return top_dev->gpu; in kfd_device_by_id()
119 if (top_dev->gpu && top_dev->gpu->adev->pdev == pdev) { in kfd_device_by_pci_dev()
120 device = top_dev->gpu; in kfd_device_by_pci_dev()
132 struct kfd_mem_properties *mem; in kfd_release_topology_device() local
138 list_del(&dev->list); in kfd_release_topology_device()
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H A Dkfd_process.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
59 /* Ordered, single-threaded workqueue for restoring evicted
62 * their BOs and result in a live-lock situation where processes
115 pdd = workarea->pdd; in kfd_sdma_activity_worker()
118 dqm = pdd->dev->dqm; in kfd_sdma_activity_worker()
119 qpd = &pdd->qpd; in kfd_sdma_activity_worker()
126 * we loop over all SDMA queues and get their counts from user-space. in kfd_sdma_activity_worker()
132 * 1. Create a temporary list of SDMA queue nodes from the qpd->queues_list, in kfd_sdma_activity_worker()
138 * from the qpd->queues_list. in kfd_sdma_activity_worker()
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H A Dcwsr_trap_handler_gfx8.asm2 * Copyright 2015-2017 Advanced Micro Devices, Inc.
24 * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex
103 …buf_rsrc2 //shared with s_save_buf_rsrc2 (conflict: should not use mem access with s_save_…
170 // ********* Handle non-CWSR traps *******************
191 // ********* End handling of non-CWSR traps *******************
226 …could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for …
237 …s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_S…
240 …s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTY…
246 /* global mem offset */
247 … 0x0 //mem offset initial valu…
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H A Dkfd_process_queue_manager.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { in get_queue_by_qid()
39 if ((pqn->q && pqn->q->properties.queue_id == qid) || in get_queue_by_qid()
40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) in get_queue_by_qid()
51 return -EINVAL; in assign_queue_slot_by_qid()
53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { in assign_queue_slot_by_qid()
55 return -ENOSPC; in assign_queue_slot_by_qid()
66 found = find_first_zero_bit(pqm->queue_slot_bitmap, in find_available_queue_slot()
73 pqm->process->pasid); in find_available_queue_slot()
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/linux/arch/mips/include/asm/sgi/
H A Dmc.h22 #define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
32 #define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
33 #define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
34 #define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
35 #define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
36 #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
64 #define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
65 #define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
75 #define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
76 #define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
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H A Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
32 * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
33 * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
14 # as a work-around:
20 - qcom,adreno
21 - amd,imageon
23 - compatible
28 - description: |
30 figure out the chip-id.
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/linux/drivers/usb/misc/sisusbvga/
H A Dsisusb.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
3 * sisusb - usb kernel driver for Net2280/SiS315 based USB2VGA dongles
83 p->header = cpu_to_le16(p->header); \
84 p->address = cpu_to_le32(p->address); \
85 p->data = cpu_to_le32(p->data); \
93 struct sisusb_urb_context { /* urb->context for outbound bulk URBs */
140 #define SISUSB_EP_GFX_IN 0x0e /* gfx std packet out(0e)/in(8e) */
143 #define SISUSB_EP_GFX_BULK_OUT 0x01 /* gfx mem bulk out/in */
146 #define SISUSB_EP_GFX_LBULK_OUT 0x03 /* gfx large mem bulk out */
148 #define SISUSB_EP_UNKNOWN_04 0x04 /* ? 4 is "OUT" ? - unused */
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/linux/drivers/gpu/drm/aspeed/
H A Daspeed_gfx_drv.c1 // SPDX-License-Identifier: GPL-2.0+
5 #include <linux/dma-mapping.h>
31 * DOC: ASPEED GFX Driver
33 * This driver is for the ASPEED BMC SoC's 'GFX' display hardware, also called
94 { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
95 { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
96 { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
115 drm->mode_config.min_width = 0; in aspeed_gfx_setup_mode_config()
116 drm->mode_config.min_height = 0; in aspeed_gfx_setup_mode_config()
117 drm->mode_config.max_width = 800; in aspeed_gfx_setup_mode_config()
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/linux/drivers/video/fbdev/
H A Dsstfb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
5 * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
16 * (enable driver on big-endian machines (hppa), ioctl fixes)
26 * add /sys/class/graphics/fbX/vgapass sysfs-interface
34 * 0x000000 - 0x3fffff : registers (4MB)
35 * 0x400000 - 0x7fffff : linear frame buffer (4MB)
36 * 0x800000 - 0xffffff : texture memory (8MB)
42 -TODO: at one time or another test that the mode is acceptable by the monitor
43 -ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
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/linux/arch/x86/kernel/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * This file contains the setup_arch() code, which handles the architecture-dependent
12 #include <linux/dma-map-ops.h>
24 #include <linux/usb/xhci-dbgp.h>
52 #include <asm/pci-direct.h>
177 * copy_edd() - Cop
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/linux/drivers/char/agp/
H A Dintel-gtt.c15 * /fairy-tale-mode off
27 #include "intel-agp.h"
28 #include <drm/intel/intel-gtt.h>
52 /* This should undo anything done in ->setup() save the unmapping
57 * For chipsets that need to support old ums (non-gem) code, this
92 #define INTEL_GTT_GEN intel_private.driver->gen
93 #define IS_G33 intel_private.driver->is_g33
94 #define IS_PINEVIEW intel_private.driver->is_pineview
95 #define IS_IRONLAKE intel_private.driver->is_ironlake
96 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
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