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/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for Cortina systems Gemini SoC
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/clock/cortina,gemini-clock.h>
8 #include <dt-bindings/reset/cortina,gemini-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
[all …]
H A Dgemini-nas4220b.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B
6 /dts-v1/;
8 #include "gemini.dtsi"
9 #include <dt-bindings/input/input.h>
12 model = "Raidsonic NAS IB-4220-B";
13 compatible = "raidsonic,ib-4220-b", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
[all …]
H A Dgemini-sl93512r.dts1 // SPDX-License-Identifier: GPL-2.0
4 * Gemini reference design, also initially called
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
9 /dts-v1/;
11 #include "gemini.dtsi"
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
16 compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini";
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
H A Dgemini-dlink-dns-313.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
6 /dts-v1/;
8 #include "gemini.dtsi"
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
14 compatible = "dlink,dns-313", "cortina,gemini";
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
H A Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include "gemini.dtsi"
9 #include <dt-bindings/input/input.h>
13 compatible = "itian,sq201", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
[all …]
H A Dgemini-ns2502.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include "gemini.dtsi"
12 model = "Edimax NS-2502";
13 compatible = "edimax,ns-2502", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 mdio-gpio0 = &mdio0;
29 stdout-path = &uart0;
33 compatible = "virtual,mdio-gpio";
[all …]
H A Dgemini-ssi1328.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include "gemini.dtsi"
13 compatible = "ssi,1328", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 mdio-gpio0 = &mdio0;
29 stdout-path = &uart0;
33 compatible = "virtual,mdio-gpio";
36 #address-cells = <1>;
[all …]
H A Dgemini-rut1xx.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include "gemini.dtsi"
9 #include <dt-bindings/input/input.h>
13 compatible = "teltonika,rut1xx", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
[all …]
H A Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
7 #include "gemini.dtsi"
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
[all …]
H A Dgemini-wbd111.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for Wiliboard WBD-111
6 /dts-v1/;
8 #include "gemini.dtsi"
9 #include <dt-bindings/input/input.h>
12 model = "Wiliboard WBD-111";
13 compatible = "wiligear,wiliboard-wbd111", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
25 stdout-path = &uart0;
[all …]
H A Dgemini-wbd222.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for Wiliboard WBD-222
6 /dts-v1/;
8 #include "gemini.dtsi"
9 #include <dt-bindings/input/input.h>
12 model = "Wiliboard WBD-222";
13 compatible = "wiligear,wiliboard-wbd222", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996-xiaomi-gemini.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
9 #include "msm8996-xiaomi-common.dtsi"
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/sound/qcom,wcd9335.h>
13 #include <dt-bindings/input/ti-drv260x.h>
17 compatible = "xiaomi,gemini", "qcom,msm8996";
18 chassis-type = "handset";
19 qcom,msm-id = <246 0x30001>;
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dfaraday,ftgpio010.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/faraday,ftgpio010.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Faraday Technology FTGPIO010 GPIO Controller
10 - Linus Walleij <linus.walleij@linaro.org>
15 - items:
16 - const: cortina,gemini-gpio
17 - const: faraday,ftgpio010
18 - items:
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu9_driver_if.h46 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
47 #define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
48 #define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
49 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
51 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
52 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
65 #define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
70 /* Gemini Modes */
[all …]
/linux/drivers/media/pci/saa7146/
H A Dhexium_gemini.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 hexium_gemini.c - v4l2 driver for Hexium Gemini frame grabber cards
16 #include <media/drv-intf/saa7146_vv.h>
103 { 0x01, 0x52 }, { 0x12, 0x64 }, { 0x2D, 0x2C }, { 0x2E, 0x9B }, { -1 , 0xFF }
107 { 0x01, 0x53 }, { 0x12, 0x04 }, { 0x2D, 0x23 }, { 0x2E, 0x81 }, { -1 , 0xFF }
111 { 0x01, 0x52 }, { 0x12, 0x64 }, { 0x2D, 0x2C }, { 0x2E, 0x9B }, { -1 , 0xFF }
126 /* fixme: h_offset = 0 for Hexium Gemini *Dual*, which
153 struct hexium *hexium = (struct hexium *) dev->ext_priv; in hexium_init_done()
162 …if (0 != i2c_smbus_xfer(&hexium->i2c_adapter, 0x6c, 0, I2C_SMBUS_WRITE, i, I2C_SMBUS_BYTE_DATA, &d… in hexium_init_done()
178 …if (0 != i2c_smbus_xfer(&hexium->i2c_adapter, 0x6c, 0, I2C_SMBUS_WRITE, hexium_input_select[input]… in hexium_set_input()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_navi10.h50 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
51 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
52 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
53 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
54 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
55 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
56 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
57 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
58 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
59 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
[all …]
/linux/drivers/mtd/maps/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Support non-linear mappings of flash chips"
21 with config options or at run-time.
79 bool "Baikal-T1 Boot ROMs OF-based physical memory map handling"
86 This provides some extra DT physmap parsing for the Baikal-T1
87 platforms, some detection and setting up ROMs-specific accessors.
90 bool "ARM Versatile OF-based physical memory map handling"
100 bool "Cortina Gemini OF-based physical memory map handling"
106 This provides some extra DT physmap parsing for the Gemini
111 bool "Intel IXP4xx OF-based physical memory map handling"
[all …]
H A Dphysmap-core.c1 // SPDX-License-Identifier: GPL-2.0+
8 * 031022 - [jsun] add run-time configure and partition setup
17 * GPIO address extension:
23 * Copyright © 2005-2009 Analog Devices Inc.
43 #include <linux/gpio/consumer.h>
45 #include "physmap-bt1-rom.h"
46 #include "physmap-gemini.h"
47 #include "physmap-ixp4xx.h"
48 #include "physmap-versatile.h"
74 if (info->cmtd) { in physmap_flash_remove()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_v13_0_7_pptable.h32 …RDWAREDC 0x4 // This cap indicates whether DC mode notificaiton is done by GPIO pin directly.
37 // SMU_13_0_7_PP_THERMALCONTROLLER - Thermal Controller Type
186 …uint16_t boost_power_limit; //For Gemini Board, when the slave adapter is in BACO mode, the master…
H A Dsmu_v14_0_2_pptable.h36 …REDC 0x4 // This cap indicates whether DC mode notificaiton is done by GPIO pin directly.
43 // SMU_14_0_2_PP_THERMALCONTROLLER - Thermal Controller Type
162 …uint16_t boost_power_limit; // For Gemini Board, when the slave adapte…
169 … // PPTable_t in driver_if.h -- as requested by PMFW, this offset should start a…
H A Dsmu_v11_0_7_pptable.h32 … 0x4 // This cap indicates whether DC mode notificaiton is done by GPIO pin directly.
37 // SMU_11_0_7_PP_THERMALCONTROLLER - Thermal Controller Type
186 …uint16_t boost_power_limit; //For Gemini Board, when the slave adapter is in BAC…
/linux/drivers/pinctrl/intel/
H A Dpinctrl-geminilake.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Gemini Lake SoC pinctrl/GPIO driver
16 #include "pinctrl-intel.h"
454 .name = "geminilake-pinctrl",
473 MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver");
/linux/drivers/net/wireless/ti/wl1251/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 1998-2007 Texas Instruments Incorporated
98 Host Interrupt Mask Register - 32bit (RW)
99 ------------------------------------------
102 0 - RX0 - Rx first dubble buffer Data Interrupt
103 1 - TXD - Tx Data Interrupt
104 2 - TXXFR - Tx Transfer Interrupt
105 3 - RX1 - Rx second dubble buffer Data Interrupt
106 4 - RXXFR - Rx Transfer Interrupt
107 5 - EVENT_A - Event Mailbox interrupt
[all …]
/linux/drivers/net/wireless/ti/wl12xx/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
25 Host Software Reset - 32bit RW
26 ------------------------------------------
28 0 SOFT_RESET Soft Reset - When this bit is set,
35 (not self-clearing), the Wlan hardware
48 Host Interrupt Mask Register - 32bit (RW)
49 ------------------------------------------
52 0 - RX0 - Rx first dubble buffer Data Interrupt
53 1 - TXD - Tx Data Interrupt
[all …]

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