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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dqcom,ssc-block-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
10 - Michael Srba <Michael.Srba@seznam.cz>
14 need to be turned on in a sequence before communication over the AHB bus
27 - const: qcom,msm8998-ssc-block-bus
28 - const: qcom,ssc-block-bus
32 - description: SSCAON_CONFIG0 registers
[all …]
H A Dsimple-pm-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bus/simple-pm-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple Power-Managed Bus
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 A Simple Power-Managed Bus is a transparent bus that doesn't need a real
16 However, its bus controller is part of a PM domain, or under the control
17 of a functional clock. Hence, the bus controller's PM domain and/or
18 clock must be enabled for child devices connected to the bus (either
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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dqcom,msm8996-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Sibi Sankar <quic_sibis@quicinc.com>
20 - qcom,msm8996-mss-pil
21 - qcom,msm8998-mss-pil
22 - qcom,sdm660-mss-pil
23 - qcom,sdm845-mss-pil
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H A Dqcom,sc7180-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <quic_sibis@quicinc.com>
19 - qcom,sc7180-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8660.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
[all …]
H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
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H A Dqcom-ipq4019.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
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H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
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H A Dqcom-mdm9615.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
13 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
15 #include <dt-bindings/mfd/qcom-rpm.h>
16 #include <dt-bindings/soc/qcom,gsbi.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dqcom,sdm660.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM660 Network-O
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,sdm845-dpu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dp
[all...]
H A Dqcom,mdp5.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15 - Rob Clark <robdclark@gmail.com>
20 - const: qcom,mdp5
22 - items:
23 - enum:
24 - qcom,apq8084-mdp5
25 - qcom,msm8226-mdp5
[all …]
H A Dqcom,sm6350-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6350-mdss
24 - description: Display AHB clock from gcc
25 - description: Display AXI clock from gcc
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H A Dmdp5.txt10 - compatible:
11 * "qcom,mdp5" - MDP5
12 - reg: Physical base address and length of the controller's registers.
13 - reg-names: The names of register regions. The following regions are required:
15 - interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
16 - clocks: device clocks. See ../clocks/clock-bindings.txt for details.
17 - clock-names: the following clocks are required.
18 - * "bus"
19 - * "iface"
20 - * "core"
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H A Ddpu-qcm2290.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Loic Poulain <loic.poulain@linaro.org>
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
20 - const: qcom,qcm2290-mdss
25 reg-names:
28 power-domains:
33 - description: Display AHB clock from gcc
[all …]
H A Dqcom,mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
[all …]
H A Dqcom,sm8350-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mds
[all...]
H A Dqcom,sm6375-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
13 SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6375-mdss
24 - description: Display AHB clock from gcc
25 - description: Display AHB clock
[all …]
H A Dqcom,qcm2290-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mds
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dipq8074.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
21 #clock-cells = <0>;
25 compatible = "fixed-clock";
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H A Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-msm.txt1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
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/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dqcom,scm.txt9 - compatible: must contain one of the following:
10 * "qcom,scm-apq8064"
11 * "qcom,scm-apq8084"
12 * "qcom,scm-ipq4019"
13 * "qcom,scm-ipq806x"
14 * "qcom,scm-ipq8074"
15 * "qcom,scm-mdm9607"
16 * "qcom,scm-msm8226"
17 * "qcom,scm-msm8660"
18 * "qcom,scm-msm8916"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dqcom,iommu.txt3 Qualcomm "B" family devices which are not compatible with arm-smmu have
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
13 "qcom,msm8953-iommu"
15 Followed by "qcom,msm-iommu-v1".
17 - clock-names : Should be a pair of "iface" (required for IOMMUs
18 register group access) and "bus" (required for
19 the IOMMUs underlying bus access).
21 - clocks : Phandles for respective clocks described by
[all …]

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