Searched +full:gbe1 +full:- +full:50 (Results 1 – 6 of 6) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/9 compatible = "ti,keystone-navigator-qmss";10 dma-coherent;11 #address-cells = <1>;12 #size-cells = <1>;15 queue-range = <0 0x2000>;20 #address-cells = <1>;21 #size-cells = <1>;24 managed-queues = <0 0x2000>;[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/9 compatible = "ti,keystone-navigator-qmss";10 dma-coherent;11 #address-cells = <1>;12 #size-cells = <1>;15 queue-range = <0 0x4000>;20 #address-cells = <1>;21 #size-cells = <1>;24 managed-queues = <0 0x2000>;[all …]
1 // SPDX-License-Identifier: GPL-2.011 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.41 * since the registers are 16-bit.184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))187 * lane0: USB3/GbE1 PHY Configuration 1208 * lane0: USB3/GbE1 PHY Status 1221 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */263 void __iomem *lane0_phy_regs; /* USB3 and GbE1 */301 /*-----------------------------------------------------------*/[all …]
31 #include "ip32-common.h"36 crime->control; in flush_crime_bus()41 mace->perif.ctrl.misc; in flush_mace_bus()47 * IP0 -> software (ignored)48 * IP1 -> software (ignored)49 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???50 * IP3 -> (irq1) X unknown51 * IP4 -> (irq2) X unknown52 * IP5 -> (irq3) X unknown53 * IP6 -> (irq4) X unknown[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT4 #include <dt-bindings/phy/phy-imx8-pcie.h>5 #include <dt-bindings/net/ti-dp83867.h>26 stdout-path = &uart4;30 compatible = "gpio-usb-b-connector", "usb-b-connector";31 pinctrl-names = "default";32 pinctrl-0 = <&pinctrl_usb0_id>;33 id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;35 self-powered;37 vbus-supply = <®_usb0_vbus>;[all …]