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/linux/drivers/clk/qcom/
H A Dclk-branch.h13 * struct clk_branch - gating clock with status bit and dynamic hardware gating
15 * @hwcg_reg: dynamic hardware clock gating register
16 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
42 * struct clk_mem_branch - gating clock which are associated with memories
44 * @mem_enable_reg: branch clock memory gating register
49 * @branch: branch clock gating handle
H A Dclk-krait.c32 /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */ in __krait_mux_set_sel()
46 /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */ in __krait_mux_set_sel()
/linux/sound/soc/intel/catpt/
H A Ddsp.c166 /* wait for SRAM power gating to propagate */ in catpt_dsp_set_srampge()
204 /* disable core clock gating */ in catpt_dsp_update_srampge()
209 /* enable core clock gating */ in catpt_dsp_update_srampge()
353 /* disable core clock gating */
366 /* switch clock gating */ in catpt_dsp_power_down()
374 /* SRAM power gating all */ in catpt_dsp_power_down()
386 /* enable core clock gating */ in catpt_dsp_power_down()
398 /* disable core clock gating */
401 /* switch clock gating */ in catpt_dsp_power_up()
408 /* SRAM power gating non in catpt_dsp_power_up()
[all...]
/linux/drivers/soc/tegra/
H A Dflowctrl.c84 /* pwr gating on wfe */ in flowctrl_cpu_suspend_enter()
99 * power-gating (like memory running off PLLP), in flowctrl_cpu_suspend_enter()
103 * while wfe for the power-gating, just like it in flowctrl_cpu_suspend_enter()
108 /* pwr gating on wfi */ in flowctrl_cpu_suspend_enter()
115 reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ in flowctrl_cpu_suspend_enter()
/linux/drivers/clk/bcm/
H A Dclk-kona.h98 * Gating control and status is managed by a 32-bit gate register.
100 * There are several types of gating available:
103 * - hardware-only gating (auto-gating)
108 * - software-only gating
109 * Auto-gating is not available for this type of clock.
113 * To ensure a change to the gating status is complete, the
116 * - selectable hardware or software gating
117 * Gating for this type of clock can be configured to be either
125 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
H A Dclk-iproc.h22 /* PLL that requires gating through ASIU */
98 * Clock gating control at the top ASIU level
/linux/drivers/pmdomain/st/
H A Dste-ux500-pm-domain.c23 * Handle the gating of the PM domain regulator here. in pd_power_off()
27 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_off()
39 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_on()
/linux/drivers/gpu/drm/gma500/
H A Dpsb_device.c89 u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL); in psb_init_pm() local
90 gating &= ~3; /* Disable 2D clock gating */ in psb_init_pm()
91 gating |= 1; in psb_init_pm()
92 PSB_WSGX32(gating, PSB_CR_CLKGATECTL); in psb_init_pm()
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.h36 * 0=Default, use auto-clock gating to save power;
37 * 1=use free-run clock, disable auto-clock gating, for debug mode.
39 * have auto-clock gating. 1=Enable pixclk. Default 0.
41 * have auto-clock gating. 1=Enable sysclk. Default 0.
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c530 * vcn_v5_0_0_disable_static_power_gating - disable VCN static power gating
534 * Disable static power gating for VCN block
598 * vcn_v5_0_0_enable_static_power_gating - enable VCN static power gating
602 * Enable static power gating for VCN block
645 * vcn_v5_0_0_disable_clock_gating - disable VCN clock gating
649 * Disable clock gating for VCN block
658 * vcn_v5_0_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
664 * Disable clock gating for VCN block with dpg mode
675 * vcn_v5_0_0_enable_clock_gating - enable VCN clock gating
679 * Enable clock gating for VCN block
[all …]
H A Dhdp_v7_0.c50 /* disable clock and power gating before any changing */ in hdp_v7_0_update_clock_gating()
71 /* only one clock gating mode (LS/DS/SD) can be enabled */ in hdp_v7_0_update_clock_gating()
H A Dvcn_v3_0.c772 * vcn_v3_0_disable_clock_gating - disable VCN clock gating
776 * Disable clock gating for VCN block
916 /* enable sw clock gating control */ in vcn_v3_0_clock_gating_dpg_mode()
946 /* turn off clock gating */ in vcn_v3_0_clock_gating_dpg_mode()
950 /* turn on SUVD clock gating */ in vcn_v3_0_clock_gating_dpg_mode()
960 * vcn_v3_0_enable_clock_gating - enable VCN clock gating
964 * Enable clock gating for VCN block
1040 /* enable dynamic power gating mode */ in vcn_v3_0_start_dpg_mode()
1049 /* enable clock gating */ in vcn_v3_0_start_dpg_mode()
1211 /* disable VCN power gating */ in vcn_v3_0_start()
[all …]
H A Dhdp_v6_0.c59 /* disable clock and power gating before any changing */ in hdp_v6_0_update_clock_gating()
80 /* only one clock gating mode (LS/DS/SD) can be enabled */ in hdp_v6_0_update_clock_gating()
/linux/sound/hda/common/
H A Djack.c213 /* A gating jack indicates the jack is invalid if gating is unplugged */ in jack_detect_update()
382 * snd_hda_jack_set_gating_jack - Set gating jack.
385 * @gating_nid: gating pin NID in snd_hda_jack_set_gating_jack()
387 * Indicates the gated jack is only valid when the gating jack is plugged. in snd_hda_jack_set_gating_jack() local
393 struct hda_jack_tbl *gating = in snd_hda_jack_set_gating_jack()
398 if (!gated || !gating) in snd_hda_jack_set_gating_jack()
402 gating->gated_jack = gated_nid;
487 * to make sure that all gating jacks properly have been set in snd_hda_jack_report_sync()
/linux/drivers/media/dvb-frontends/
H A Ddib3000mc.h48 int gating);
69 int gating) in dib3000mc_get_tuner_i2c_master() argument
H A Ddib9000.h35 …pter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating);
52 …apter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating) in dib9000_get_i2c_master() argument
/linux/sound/soc/sof/intel/
H A Dhda-ipc.h43 /* Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */
45 /* Prevent power gating (0 - deep power state transitions allowed) */
H A Dbdw.c121 /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ in bdw_set_dsp_D0()
162 /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */ in bdw_set_dsp_D0()
174 /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */ in bdw_set_dsp_D0()
188 * set default power gating control, enable power gating control for in bdw_set_dsp_D0()
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml79 Defines the memory self-refresh and controller clock gating idle period.
81 arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
302 arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
330 Defines the self-refresh and memory-controller clock gating disable
/linux/Documentation/devicetree/bindings/clock/
H A Dimx8qxp-lpcg.yaml7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
17 This level of clock gating is provided after the clocks are generated
/linux/arch/arm/mach-socfpga/
H A Dself-refresh.S48 /* Enable dynamic clock gating in the Power Control Register. */
115 /* Disable dynamic clock gating in the Power Control Register. */
/linux/drivers/media/platform/samsung/s5p-mfc/
H A Ds5p_mfc_pm.c82 /* prepare for software clock gating */ in s5p_mfc_power_on()
97 /* finish software clock gating */ in s5p_mfc_power_off()
/linux/Documentation/devicetree/bindings/power/
H A Dfsl,imx-gpcv2.yaml13 The i.MX7S/D General Power Control (GPC) block contains Power Gating
19 described as subnodes of the power gating controller 'pgc' node.
/linux/drivers/clk/mvebu/
H A Darmada-39x.c135 * Clock Gating Control
155 CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
H A Dmv98dx3236.c155 * Clock Gating Control
171 of_find_compatible_node(NULL, NULL, "marvell,mv98dx3236-gating-clock"); in mv98dx3236_clk_init()

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