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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dbrcm,bcm6368-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm6368-pinctr
[all...]
H A Dbrcm,bcm6362-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm6362-pinctr
[all...]
H A Dbrcm,bcm63268-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctr
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H A Dbrcm,bcm6318-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm6318-pinctr
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8916-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 blsp1_uart1_default: blsp1-uart1-default-state {
10 pins = "gpio0", "gpio1", "gpio2", "gpio3";
11 function = "blsp_uart1";
13 drive-strength = <16>;
14 bias-disable;
17 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
18 pins = "gpio0", "gpio1", "gpio2", "gpio3";
19 function = "gpio";
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H A Dmsm8996-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
11 pins = "gpio54";
12 function = "gpio";
16 pins = "gpio54";
17 drive-strength = <2>; /* 2 mA */
18 bias-pull-down; /* pull down */
19 input-enable;
27 pins = "gpio64";
28 function = "gpio";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
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H A Dexynos990-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Samsung Exynos 990 pin-mux and pin-config device tree source
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&gic>;
[all …]
H A Dexynos2200-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Samsung's Exynos 2200 SoC pin-mux and pin-config device tree source
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&gic>;
[all …]
H A Dexynos8895-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Samsung's Exynos 8895 SoC pin-mux and pin-config device tree source
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "exynos-pinctrl.h"
12 gph0: gph0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gph1: gph1-gpio-bank {
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H A Dexynos7870-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7870 SoC pin-mux and pin-config device tree source
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include "exynos-pinctrl.h"
13 etc0: etc0-gpio-bank {
14 gpio-controller;
15 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
21 etc1: etc1-gpio-bank {
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H A Dexynos7885-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 etc0: etc0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
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/freebsd/sys/contrib/device-tree/src/mips/mobileye/
H A Deyeq5-pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 * pin configuration node per function.
9 timer0_pins: timer0-pins {
10 function = "timer0";
11 pins = "PA0", "PA1";
13 timer1_pins: timer1-pins {
14 function = "timer1";
15 pins = "PA2", "PA3";
17 timer2_pins: timer2-pins {
18 function = "timer2";
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Ds3c64xx-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
26 gpb: gpb-gpio-bank {
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H A Ds5pv210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source - pin control-related
6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
15 #include "s5pv210-pinctrl.h"
18 pin- ## _pi
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H A Dexynos4x12-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
16 samsung,pins = #_pin; \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dbrcm,bcm6368-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpi
[all...]
H A Dbrcm,bcm6362-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpi
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2166x-pinctrl.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
10 bsc1_pins: bsc1-pins {
11 bsc1clk-grp0 {
12 pins = "bsc1clk";
13 function = "alt1"; /* BSC1CLK */
16 bsc1dat-grp0 {
17 pins = "bsc1dat";
18 function = "alt1"; /* BSC1DAT */
23 bsc2_pins: bsc2-pins {
24 bsc2clk-grp0 {
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-apq8064-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 sdcc1_default_state: sdcc1-default-state {
5 clk-pins {
6 pins = "sdc1_clk";
7 drive-strength = <16>;
8 bias-disable;
11 cmd-pins {
12 pins = "sdc1_cmd";
13 drive-strength = <10>;
14 bias-pull-up;
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-nyan-blaze.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra124-nyan.dtsi"
6 #include "tegra124-nyan-blaze-emc.dtsi"
10 compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9",
11 "google,nyan-blaze-rev8", "google,nyan-blaze-rev7",
12 "google,nyan-blaze-rev6", "google,nyan-blaze-rev5",
13 "google,nyan-blaze-rev4", "google,nyan-blaze-rev3",
14 "google,nyan-blaze-rev2", "google,nyan-blaze-rev1",
15 "google,nyan-blaze-rev0", "google,nyan-blaze",
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H A Dtegra124-nyan-big.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra124-nyan.dtsi"
6 #include "tegra124-nyan-big-emc.dtsi"
9 model = "Acer Chromebook 13 CB5-311";
10 compatible = "google,nyan-big-rev7", "google,nyan-big-rev6",
11 "google,nyan-big-rev5", "google,nyan-big-rev4",
12 "google,nyan-big-rev3", "google,nyan-big-rev2",
13 "google,nyan-big-rev1", "google,nyan-big-rev0",
14 "google,nyan-big", "google,nyan", "nvidia,tegra124";
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H A Dtegra30-beaver.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
19 stdout-pat
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/google/
H A Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nuvoton/
H A Dnuvoton-common-npcm7xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&gic>;
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <25000000>;
[all …]

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