Searched +full:fu540 +full:- +full:c000 +full:- +full:clint (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Palmer Dabbelt <palmer@dabbelt.com>11 - Anup Patel <anup.patel@wdc.com>14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor16 interrupts. It directly connects to the timer and inter-processor interrupt17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)2 /* Copyright (c) 2020-2021 Microchip Technology Inc */4 /dts-v1/;5 #include "dt-bindings/clock/microchip,mpfs-clock.h"8 #address-cells = <2>;9 #size-cells = <2>;14 #address-cells = <1>;15 #size-cells = <0>;16 timebase-frequency = <1000000>;21 i-cache-block-size = <64>;[all …]