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/linux/sound/soc/codecs/
H A Dadau-utils.c15 int adau_calc_pll_cfg(unsigned int freq_in, unsigned int freq_out, in adau_calc_pll_cfg() argument
27 if (freq_out % freq_in != 0) { in adau_calc_pll_cfg()
28 div = DIV_ROUND_UP(freq_in, 13500000); in adau_calc_pll_cfg()
29 freq_in /= div; in adau_calc_pll_cfg()
30 r = freq_out / freq_in; in adau_calc_pll_cfg()
31 i = freq_out % freq_in; in adau_calc_pll_cfg()
32 j = gcd(i, freq_in); in adau_calc_pll_cfg()
34 m = freq_in / j; in adau_calc_pll_cfg()
37 r = freq_out / freq_in; in adau_calc_pll_cfg()
H A Drl6231.c132 * @freq_in: external clock provided to codec.
140 int rl6231_pll_calc(const unsigned int freq_in, in rl6231_pll_calc() argument
147 unsigned int red_t = abs(freq_out - freq_in); in rl6231_pll_calc()
151 if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in) in rl6231_pll_calc()
155 if (freq_in == pll_preset_table[i].pll_in && in rl6231_pll_calc()
173 div_t = gcd(freq_in, freq_out); in rl6231_pll_calc()
175 div = find_best_div(freq_in, f_max, div_t); in rl6231_pll_calc()
176 f_in = freq_in / div; in rl6231_pll_calc()
H A Dwm8960.c53 unsigned int freq_in, unsigned int freq_out);
145 int freq_in; member
691 * @freq_in: input frequency used to derive freq out via PLL
702 int wm8960_configure_pll(struct snd_soc_component *component, int freq_in, in wm8960_configure_pll() argument
712 closest = freq_in; in wm8960_configure_pll()
731 if (!is_pll_freq_available(freq_in, freq_out)) in wm8960_configure_pll()
757 int freq_out, freq_in; in wm8960_configure_clocking() local
775 if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) { in wm8960_configure_clocking()
780 freq_in = wm8960->freq_in; in wm8960_configure_clocking()
790 freq_out = freq_in; in wm8960_configure_clocking()
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H A Dwm8995.c1724 int freq_in, int freq_out) in wm8995_get_fll_config() argument
1729 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); in wm8995_get_fll_config()
1733 while (freq_in > 13500000) { in wm8995_get_fll_config()
1735 freq_in /= 2; in wm8995_get_fll_config()
1740 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); in wm8995_get_fll_config()
1752 if (freq_in > 1000000) { in wm8995_get_fll_config()
1754 } else if (freq_in > 256000) { in wm8995_get_fll_config()
1756 freq_in *= 2; in wm8995_get_fll_config()
1757 } else if (freq_in > 128000) { in wm8995_get_fll_config()
1759 freq_in *= 4; in wm8995_get_fll_config()
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H A Drt1019.c325 unsigned int freq_in, unsigned int freq_out) in rt1019_set_dai_pll() argument
332 if (!freq_in || !freq_out) { in rt1019_set_dai_pll()
339 if (source == rt1019->pll_src && freq_in == rt1019->pll_in && in rt1019_set_dai_pll()
359 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); in rt1019_set_dai_pll()
361 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt1019_set_dai_pll()
382 rt1019->pll_in = freq_in; in rt1019_set_dai_pll()
H A Drt1318.c791 static int rt1318_pll_calc(const unsigned int freq_in, in rt1318_pll_calc() argument
797 int red_t = abs(freq_out - freq_in); in rt1318_pll_calc()
800 if (RT1318_PLL_INP_MAX < freq_in || RT1318_PLL_INP_MIN > freq_in) in rt1318_pll_calc()
804 if (freq_in == pll_preset_table[i].pll_in && in rt1318_pll_calc()
823 in_t = freq_in / (k_bypass ? 1 : (k + 2)); in rt1318_pll_calc()
867 unsigned int freq_in, unsigned int freq_out) in rt1318_set_dai_pll() argument
874 if (!freq_in || !freq_out) { in rt1318_set_dai_pll()
881 if (source == rt1318->pll_src && freq_in == rt1318->pll_in && in rt1318_set_dai_pll()
923 ret = rt1318_pll_calc(freq_in, freq_out, &pll_code); in rt1318_set_dai_pll()
925 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); in rt1318_set_dai_pll()
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H A Drt1016.c454 int pll_id, int source, unsigned int freq_in, in rt1016_set_component_pll() argument
461 if (!freq_in || !freq_out) { in rt1016_set_component_pll()
470 if (source == rt1016->pll_src && freq_in == rt1016->pll_in && in rt1016_set_component_pll()
490 ret = rl6231_pll_calc(freq_in, freq_out * 4, &pll_code); in rt1016_set_component_pll()
492 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt1016_set_component_pll()
509 rt1016->pll_in = freq_in; in rt1016_set_component_pll()
H A Dak4375.c255 unsigned int freq_in, freq_out; in ak4375_hw_params() local
264 freq_in = 32 * ak4375->rate / (ak4375->pld + 1); in ak4375_hw_params()
271 return snd_soc_dai_set_pll(dai, 0, 0, freq_in, freq_out); in ak4375_hw_params()
275 unsigned int freq_in, unsigned int freq_out) in ak4375_dai_set_pll() argument
350 plm = freq_out / freq_in - 1; in ak4375_dai_set_pll()
362 ak4375->rate, mclk, freq_in, freq_out, ak4375->pld, plm, mdiv, div); in ak4375_dai_set_pll()
H A Drt1308.c616 int pll_id, int source, unsigned int freq_in, in rt1308_set_component_pll() argument
623 if (source == rt1308->pll_src && freq_in == rt1308->pll_in && in rt1308_set_component_pll()
627 if (!freq_in || !freq_out) { in rt1308_set_component_pll()
656 freq_in = 25000000; in rt1308_set_component_pll()
663 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); in rt1308_set_component_pll()
665 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt1308_set_component_pll()
679 rt1308->pll_in = freq_in; in rt1308_set_component_pll()
H A Dwm8994.c2123 int freq_in, int freq_out) in wm8994_get_fll_config() argument
2128 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); in wm8994_get_fll_config()
2132 while (freq_in > 13500000) { in wm8994_get_fll_config()
2134 freq_in /= 2; in wm8994_get_fll_config()
2139 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); in wm8994_get_fll_config()
2151 if (freq_in > 1000000) { in wm8994_get_fll_config()
2153 } else if (freq_in > 256000) { in wm8994_get_fll_config()
2155 freq_in *= 2; in wm8994_get_fll_config()
2156 } else if (freq_in > 128000) { in wm8994_get_fll_config()
2158 freq_in *= 4; in wm8994_get_fll_config()
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H A Dwm8900.c746 int fll_id, unsigned int freq_in, unsigned int freq_out) in wm8900_set_fll() argument
751 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out) in wm8900_set_fll()
759 if (!freq_in || !freq_out) { in wm8900_set_fll()
764 wm8900->fll_in = freq_in; in wm8900_set_fll()
770 if (fll_factors(&fll_div, freq_in, freq_out) != 0) in wm8900_set_fll()
773 wm8900->fll_in = freq_in; in wm8900_set_fll()
810 int source, unsigned int freq_in, unsigned int freq_out) in wm8900_set_dai_pll() argument
812 return wm8900_set_fll(codec_dai->component, pll_id, freq_in, freq_out); in wm8900_set_dai_pll()
H A Drt1305.c791 int pll_id, int source, unsigned int freq_in, in rt1305_set_component_pll() argument
798 if (source == rt1305->pll_src && freq_in == rt1305->pll_in && in rt1305_set_component_pll()
802 if (!freq_in || !freq_out) { in rt1305_set_component_pll()
833 freq_in = 98304000; in rt1305_set_component_pll()
840 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); in rt1305_set_component_pll()
842 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt1305_set_component_pll()
857 rt1305->pll_in = freq_in; in rt1305_set_component_pll()
H A Dnau8822.c712 unsigned int freq_in, unsigned int freq_out) in nau8822_set_pll() argument
719 if (freq_in == pll_param->freq_in && in nau8822_set_pll()
732 ret = nau8822_calc_pll(freq_in, fs, pll_param); in nau8822_set_pll()
735 freq_in); in nau8822_set_pll()
766 pll_param->freq_in = freq_in; in nau8822_set_pll()
H A Drt1015.c841 int pll_id, int source, unsigned int freq_in, in rt1015_set_component_pll() argument
848 if (!freq_in || !freq_out) { in rt1015_set_component_pll()
857 if (source == rt1015->pll_src && freq_in == rt1015->pll_in && in rt1015_set_component_pll()
877 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); in rt1015_set_component_pll()
879 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt1015_set_component_pll()
894 rt1015->pll_in = freq_in; in rt1015_set_component_pll()
H A Dadau-utils.h5 int adau_calc_pll_cfg(unsigned int freq_in, unsigned int freq_out,
H A Dwm8580.c461 int source, unsigned int freq_in, unsigned int freq_out) in wm8580_set_dai_pll() argument
492 if (freq_in && freq_out) { in wm8580_set_dai_pll()
493 ret = pll_factors(&pll_div, freq_out, freq_in); in wm8580_set_dai_pll()
498 state->in = freq_in; in wm8580_set_dai_pll()
506 if (!freq_in || !freq_out) in wm8580_set_dai_pll()
H A Drl6231.h28 int rl6231_pll_calc(const unsigned int freq_in,
H A Dnau8540.c667 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. in nau8540_calc_fll_param()
668 * FREF = freq_in / NAU8540_FLL_REF_DIV_MASK in nau8540_calc_fll_param()
758 unsigned int freq_in, unsigned int freq_out) in nau8540_set_pll() argument
793 ret = nau8540_calc_fll_param(freq_in, fs, &fll_param); in nau8540_set_pll()
795 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in); in nau8540_set_pll()
H A Drt5514.c897 unsigned int freq_in, unsigned int freq_out) in rt5514_set_dai_pll() argument
904 if (!freq_in || !freq_out) { in rt5514_set_dai_pll()
916 if (source == rt5514->pll_src && freq_in == rt5514->pll_in && in rt5514_set_dai_pll()
936 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); in rt5514_set_dai_pll()
938 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt5514_set_dai_pll()
953 rt5514->pll_in = freq_in; in rt5514_set_dai_pll()
H A Drt5616.c1095 unsigned int freq_in, unsigned int freq_out) in rt5616_set_dai_pll() argument
1102 if (source == rt5616->pll_src && freq_in == rt5616->pll_in && in rt5616_set_dai_pll()
1106 if (!freq_in || !freq_out) { in rt5616_set_dai_pll()
1134 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); in rt5616_set_dai_pll()
1136 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt5616_set_dai_pll()
1151 rt5616->pll_in = freq_in; in rt5616_set_dai_pll()
H A Drt5660.c1008 unsigned int freq_in, unsigned int freq_out) in rt5660_set_dai_pll() argument
1015 if (source == rt5660->pll_src && freq_in == rt5660->pll_in && in rt5660_set_dai_pll()
1019 if (!freq_in || !freq_out) { in rt5660_set_dai_pll()
1045 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); in rt5660_set_dai_pll()
1047 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt5660_set_dai_pll()
1061 rt5660->pll_in = freq_in; in rt5660_set_dai_pll()
/linux/drivers/mfd/
H A Dtwl6040.c369 unsigned int freq_in, unsigned int freq_out) in twl6040_set_pll() argument
412 switch (freq_in) { in twl6040_set_pll()
427 "freq_in %d not supported\n", freq_in); in twl6040_set_pll()
443 if (twl6040->mclk_rate != freq_in) { in twl6040_set_pll()
446 switch (freq_in) { in twl6040_set_pll()
469 "freq_in %d not supported\n", freq_in); in twl6040_set_pll()
493 twl6040->mclk_rate = freq_in; in twl6040_set_pll()
/linux/sound/soc/intel/avs/boards/
H A Drt5682.c149 int pll_source, freq_in, freq_out; in avs_rt5682_hw_params() local
155 freq_in = 24000000; in avs_rt5682_hw_params()
157 freq_in = 19200000; in avs_rt5682_hw_params()
160 freq_in = params_rate(params) * 50; in avs_rt5682_hw_params()
165 ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL1, pll_source, freq_in, freq_out); in avs_rt5682_hw_params()
/linux/sound/soc/
H A Dsoc-dai.c96 * @freq_in: PLL input clock frequency in Hz
102 unsigned int freq_in, unsigned int freq_out) in snd_soc_dai_set_pll() argument
109 freq_in, freq_out); in snd_soc_dai_set_pll()
112 freq_in, freq_out); in snd_soc_dai_set_pll()
/linux/drivers/media/tuners/
H A Dtda18271-fe.c430 u32 *freq_in, u32 *freq_out) in tda18271_powerscan() argument
439 freq = *freq_in; in tda18271_powerscan()
472 *freq_out = *freq_in; in tda18271_powerscan()
478 freq = *freq_in + (sgn * count) + 1000000; in tda18271_powerscan()
516 tda_cal("bcal = %d, freq_in = %d, freq_out = %d (freq = %d)\n", in tda18271_powerscan()
517 bcal, *freq_in, *freq_out, freq); in tda18271_powerscan()

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