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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-qcom-hw.txt8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
27 each frequency domain.
28 - reg-names
31 Definition: Frequency domain name i.e.
32 "freq-domain0", "freq-domain1".
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H A Dcpufreq-qcom-hw.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 interrupt-parent = <&intc>;
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H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
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H A Dsm6375.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
8 #include <dt-bindings/clock/qcom,sm6375-gpucc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/firmware/qcom,scm.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
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H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
14 #include <dt-bindings/interconnect/qcom,sm6115.h>
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H A Dqdu1000.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
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H A Dsm6350.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
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H A Dsm8350.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
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/freebsd/sys/dev/clk/
H A Dclk.c1 /*-
66 static int clknode_method_recalc_freq(struct clknode *clk, uint64_t *freq);
87 * Clock node - basic element for modeling SOC clock graph. It holds the clock
95 struct clkdom *clkdom; /* Owning clock domain */
96 TAILQ_ENTRY(clknode) clkdom_link; /* Domain list entry */
102 int parent_idx; /* Parent index or -1 */
115 intptr_t id; /* Per domain unique id */
122 uint64_t freq; /* Actual frequency */ member
138 * Clock domain - a group of clocks provided by one clock device.
142 TAILQ_ENTRY(clkdom) link; /* Global domain list entry */
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H A Dclk_fixed.c1 /*-
53 static int clknode_fixed_recalc(struct clknode *clk, uint64_t *freq);
59 uint64_t freq; member
80 if (sc->freq == 0) in clknode_fixed_init()
86 clknode_fixed_recalc(struct clknode *clk, uint64_t *freq) in clknode_fixed_recalc() argument
92 if ((sc->mult != 0) && (sc->div != 0)) in clknode_fixed_recalc()
93 *freq = (*freq / sc->div) * sc->mult; in clknode_fixed_recalc()
95 *freq = sc->freq; in clknode_fixed_recalc()
106 if (sc->mult == 0 || sc->div == 0) { in clknode_fixed_set_freq()
109 if (*fout != sc->freq) in clknode_fixed_set_freq()
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H A Dclk.h1 /*-
38 #define CLKNODE_IDX_NONE -1 /* Not-selected index */
42 #define CLK_NODE_GLITCH_FREE 0x00000002 /* Freq can change w/o stop */
79 * Clock domain functions.
114 int clknode_get_freq(struct clknode *clknode, uint64_t *freq);
115 int clknode_set_freq(struct clknode *clknode, uint64_t freq, int flags,
117 int clknode_test_freq(struct clknode *clknode, uint64_t freq, int flags,
129 int clk_get_freq(clk_t clk, uint64_t *freq);
130 int clk_set_freq(clk_t clk, uint64_t freq, int flags);
131 int clk_test_freq(clk_t clk, uint64_t freq, int flags);
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/freebsd/sys/dev/ath/ath_hal/
H A Dah_regdomain.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2005-2006 Atheros Communications, Inc.
44 * Mask to check whether a domain is a multidomain or a single domain
49 * Enumerated Regulatory Domain Information 8 bit values indicate that
68 * for each band if it is used in ANY reg domain.
76 * domains which the ath regulatory domain code understands.
82 * with shared properties - max tx power, max antenna gain, channel width,
86 * Each regulatory domain entry in ah_regdomain_domains.h uses one
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/freebsd/sys/contrib/dev/athk/
H A Ddfs_pattern_detector.c25 * struct radar_types - contains array of patterns defined for one DFS domain
38 #define PPB_THRESH_RATE(PPB, RATE) ((PPB * RATE + 100 - RATE) / 100)
43 #define WIDTH_LOWER(X) ((X*(100-WIDTH_TOLERANCE)+50)/100)
49 (PRF2PRI(PMAX) - PRI_TOLERANCE), \
54 /* radar types as defined by ETSI EN-301-893 v1.5.1 */
74 PMIN - PRI_TOLERANCE, \
106 PMIN - PRI_TOLERANCE, \
135 * get_dfs_domain_radar_types() - get radar types for a given DFS domain
138 * Return value: radar_types ptr on success, NULL if DFS domain is not supported
145 if (dfs_domains[i]->region == region) in get_dfs_domain_radar_types()
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H A Ddfs_pattern_detector.h25 * TODO: this might need to be HW-dependent
30 * struct ath_dfs_pool_stats - DFS Statistics for global pools
43 * struct pulse_event - describing pulses reported by PHY
45 * @freq: channel frequency in MHz
52 u16 freq; member
59 * struct radar_detector_specs - detector specs for a radar pattern type
85 * struct dfs_pattern_detector - DFS pattern detector
87 * @set_dfs_domain(): set DFS domain, resets detector lines upon domain changes
115 * dfs_pattern_detector_init() - constructor for pattern detector class
116 * @param region: DFS domain to be used, can be NL80211_DFS_UNSET at creation
/freebsd/contrib/libarchive/libarchive/
H A Darchive_ppmd8.c1 /* Ppmd8.c -- PPMdI codec
2 2016-05-21 : Igor Pavlov : Public domain
3 This code is based on PPMd var.I (2002): Dmitry Shkarin : Public domain */
18 #define U2I(nu) (p->Units2Indx[(nu) - 1])
19 #define I2U(indx) (p->Indx2Units[indx])
24 #define REF(ptr) ((UInt32)((Byte *)(ptr) - (p)->Base))
32 #define SUFFIX(ctx) CTX((ctx)->Suffix)
59 #define NODE(offs) ((CPpmd8_Node *)(p->Base + (offs)))
68 p->Base = 0; in Ppmd8_Construct()
73 do { p->Units2Indx[k++] = (Byte)i; } while (--step); in Ppmd8_Construct()
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H A Darchive_ppmd_private.h1 /* Ppmd.h -- PPMD codec common code
2 2010-03-12 : Igor Pavlov : Public domain
3 This code is based on PPMd var.H (2001): Dmitry Shkarin : Public domain */
34 /* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers.
93 #define PPMD_GET_MEAN_SPEC(summ, shift, round) (((summ) + (1 << ((shift) - (round)))) >> (shift))
95 #define PPMD_UPDATE_PROB_0(prob) ((prob) + (1 << PPMD_INT_BITS) - PPMD_GET_MEAN(prob))
96 #define PPMD_UPDATE_PROB_1(prob) ((prob) - PPMD_GET_MEAN(prob))
101 #define PPMD_N4 ((128 + 3 - 1 * PPMD_N1 - 2 * PPMD_N2 - 3 * PPMD_N3) / 4)
104 /* SEE-contexts for PPM-contexts with masked symbols */
107 UInt16 Summ; /* Freq */
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/freebsd/tools/tools/ath/athrd/
H A Dathrd.c1 /*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
171 HAL_CAPABILITIES *pCap = &ahp->ah_caps; in getChannelEdges()
174 *low = pCap->halLow5GhzChan; in getChannelEdges()
175 *high = pCap->halHigh5GhzChan; in getChannelEdges()
179 *low = pCap->halLow2GhzChan; in getChannelEdges()
180 *high = pCap->halHigh2GhzChan; in getChannelEdges()
212 /* Enumerated Regulatory Domain Information 8 bit values indicate that
220 * The following regulatory domain definitions are
221 * found in the EEPROM. Each regulatory domain
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/freebsd/sys/arm64/qoriq/clk/
H A Dqoriq_clkgen.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
55 { -1, 0 }
96 if (sc->flags & QORIQ_LITTLE_ENDIAN) in qoriq_clkgen_write_4()
97 bus_write_4(sc->res, addr, htole32(val)); in qoriq_clkgen_write_4()
99 bus_write_4(sc->res, addr, htobe32(val)); in qoriq_clkgen_write_4()
110 if (sc->flags & QORIQ_LITTLE_ENDIAN) in qoriq_clkgen_read_4()
111 *val = le32toh(bus_read_4(sc->res, addr)); in qoriq_clkgen_read_4()
113 *val = be32toh(bus_read_4(sc->res, addr)); in qoriq_clkgen_read_4()
126 if (sc->flags & QORIQ_LITTLE_ENDIAN) in qoriq_clkgen_modify_4()
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/freebsd/contrib/wpa/src/common/
H A Dwpa_ctrl.h3 * Copyright (c) 2004-2017, Jouni Malinen <j@w1.fi>
16 /* wpa_supplicant control interface - fixed message prefixes */
19 #define WPA_CTRL_REQ "CTRL-REQ-"
22 #define WPA_CTRL_RSP "CTRL-RSP-"
26 #define WPA_EVENT_CONNECTED "CTRL-EVENT-CONNECTED "
28 #define WPA_EVENT_DISCONNECTED "CTRL-EVENT-DISCONNECTED "
30 #define WPA_EVENT_ASSOC_REJECT "CTRL-EVENT-ASSOC-REJECT "
32 #define WPA_EVENT_AUTH_REJECT "CTRL-EVENT-AUTH-REJECT "
34 #define WPA_EVENT_TERMINATING "CTRL-EVENT-TERMINATING "
36 #define WPA_EVENT_PASSWORD_CHANGED "CTRL-EVENT-PASSWORD-CHANGED "
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/freebsd/contrib/wpa/wpa_supplicant/
H A DREADME-HS204 This document describe how the IEEE 802.11u Interworking and Wi-Fi
7 GUI or Wi-Fi framework) is used to manage this functionality.
10 Introduction to Wi-Fi Hotspot 2.0
11 ---------------------------------
13 Hotspot 2.0 is the name of the Wi-Fi Alliance specification that is used
14 in the Wi-Fi CERTIFIED Passpoint<TM> program. More information about
17 http://www.wi-fi.org/knowledge-center/white-papers/wi-fi-certified-passpoint%E2%84%A2-new-program-w…
20 https://www.wi-fi.org/knowledge-center/published-specifications
23 standardized in IEEE Std 802.11u-2011 which is now part of the IEEE Std
24 802.11-2012.
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/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dmediatek,mt76.txt11 - "mediatek,mt7628-wmac" for MT7628/MT7688
12 - "mediatek,mt7622-wmac" for MT7622
15 - reg: Address and length of the register set for the device.
16 - interrupts: Main device interrupt
19 - power-domains: phandle to the power domain that the WMAC is part of
20 - mediatek,infracfg: phandle to the infrastructure bus fabric syscon node
24 - ieee80211-freq-limit: See ieee80211.txt
25 - mediatek,mtd-eeprom: Specify a MTD partition + offset containing EEPROM data
26 - big-endian: if the radio eeprom partition is written in big-endian, specify
28 - mediatek,eeprom-merge-otp: Merge EEPROM data with OTP data. Can be used on
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/freebsd/sys/contrib/xen/
H A Dplatform.h4 * Hardware platform operations. Intended for use by domain-0 kernel.
24 * Copyright (c) 2002-2006, K Fraser
66 * Request memory range (@mfn, @mfn+@nr_mfns-1) to have type @type.
67 * On x86, @type is an architecture-defined MTRR memory type.
70 * (x86-specific).
86 * Tear down an existing memory-range type. If @handle is remembered then it
90 * (x86-specific).
101 /* Read current type of an MTRR (x86-specific). */
124 #define QUIRK_NOIRQBALANCING 1 /* Do not restrict IO-APIC RTE targets */
125 #define QUIRK_IOAPIC_BAD_REGSEL 2 /* IO-APIC REGSEL forgets its value */
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/freebsd/sys/riscv/sifive/
H A Dsifive_prci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
85 #define PRCI_LOCK(sc) mtx_lock(&(sc)->mtx)
86 #define PRCI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
87 #define PRCI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
88 #define PRCI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
101 bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
103 bus_space_write_4((_sc)->bst, (_sc)->bsh, (_reg), (_val))
268 { "sifive,fu540-c000-prci", (uintptr_t)&fu540_prci_config },
269 { "sifive,fu740-c000-prci", (uintptr_t)&fu740_prci_config },
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