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/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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H A Dlattice-machxo2-spi.txt1 Lattice MachXO2 Slave SPI FPGA Manager
9 - compatible: should contain "lattice,machxo2-slave-spi"
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
17 #address-cells = <0x1>;
18 #size-cells = <0x1>;
24 fpga_mgr_spi: fpga-mgr@0 {
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H A Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 - $ref: fpga-bridge.yaml#
17 decouplers/fpga bridges. The controller can decouple/disable the bridges
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
24 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
28 Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
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/linux/Documentation/driver-api/fpga/
H A Dintro.rst4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
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H A Dfpga-programming.rst1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
14 * lock the region's mutex
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
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H A Dindex.rst2 FPGA Subsystem
11 fpga-mgr
12 fpga-bridge
13 fpga-region
14 fpga-programming
/linux/drivers/fpga/tests/
H A Dfpga-region-test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
12 #include <linux/fpga/fpga-bridge.h>
13 #include <linux/fpga/fpga-mgr.h>
14 #include <linux/fpga/fpga-region.h>
32 struct fpga_region *region; member
53 struct mgr_stats *stats = mgr->priv; in op_write()
55 stats->write_count++; in op_write()
61 * Fake FPGA manager that implements only the write op to count the number
64 * of the Region.
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for KUnit test suites for the FPGA subsystem
6 obj-$(CONFIG_FPGA_KUNIT_TESTS) += fpga-mgr-test.o fpga-bridge-test.o fpga-region-test.o
/linux/drivers/fpga/
H A Ddfl-fme-pr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 #include <linux/fpga/fpga-mgr.h>
24 #include <linux/fpga/fpga
52 struct fpga_region *region; dfl_fme_region_find() local
72 struct fpga_region *region; fme_pr() local
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H A Ddfl-fme-pr.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
24 * struct dfl_fme_region - FME fpga region data structure
26 * @region: platform device of the FPGA region.
28 * @port_id: indicate which port this region connected to.
31 struct platform_device *region; member
37 * struct dfl_fme_region_pdata - platform data for FME region platform device.
39 * @mgr: platform device of the FPGA manager.
40 * @br: platform device of the FPGA bridge.
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H A Ddfl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Device Feature List (DFL) Support
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
14 #include <linux/fpga-dfl.h>
44 "dfl-fme-pdata",
45 "dfl-por
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H A Ddfl-afu-region.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Accelerated Function Unit (AFU) MMIO Region Management
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
11 #include "dfl-afu.h"
14 * afu_mmio_region_init - init function for afu mmio region support
21 INIT_LIST_HEAD(&afu->region in afu_mmio_region_init()
24 for_each_region(region,afu) global() argument
30 struct dfl_afu_mmio_region *region; get_region_by_index() local
53 struct dfl_afu_mmio_region *region; afu_mmio_region_add() local
99 struct dfl_afu_mmio_region *tmp, *region; afu_mmio_region_destroy() local
117 struct dfl_afu_mmio_region *region; afu_mmio_region_get_by_index() local
151 struct dfl_afu_mmio_region *region; afu_mmio_region_get_by_offset() local
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H A Ddfl-fme-mgr.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
22 #include <linux/io-64-nonatomic-lo-hi.h>
23 #include <linux/fpga/fpga-mgr.h>
25 #include "dfl-fme-pr.h"
39 #define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */
52 /* PR data from the raw-binary file. */
111 struct device *dev = &mgr->dev; in fme_mgr_write_init()
112 struct fme_mgr_priv *priv = mgr->priv; in fme_mgr_write_init()
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/linux/Documentation/fpga/
H A Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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/linux/include/uapi/linux/
H A Dfpga-dfl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-fpga-region1 What: /sys/class/fpga_region/<region>/compat_id
5 Description: FPGA region id for compatibility check, e.g. compatibility
6 of the FPGA reconfiguration hardware and image. This value
8 FPGA region. This interface returns the compat_id value or
9 just error code -ENOENT in case compat_id is not used.
H A Dsysfs-platform-dfl-fme1 What: /sys/bus/platform/devices/dfl-fme.0/ports_num
5 Description: Read-only. One DFL FPGA device may have more than 1
7 number of ports on the FPGA device when read it.
9 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_id
13 Description: Read-only. It returns Bitstream (static FPGA region)
15 and other information of this static FPGA region.
17 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_metadata
21 Description: Read-only. It returns Bitstream (static FPGA region) meta
23 information of this static FPGA region.
25 What: /sys/bus/platform/devices/dfl-fme.0/cache_size
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/linux/Documentation/devicetree/bindings/firmware/
H A Dintel,stratix10-svc.txt3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
4 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
7 configuration data from that location and perform the FPGA configuration.
17 the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
30 - memory-region:
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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-ts4900.txt1 * Technologic Systems I2C-FPGA's GPIO controller bindings
3 This bindings describes the GPIO controller for Technologic's FPGA core.
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
8 - compatible: Should be one of the following
9 "technologic,ts4900-gpio"
10 "technologic,ts7970-gpio"
11 - reg: Physical base address of the controller and length
12 of memory mapped region.
13 - #gpio-cells: Should be two. The first cell is the pin number.
14 - gpio-controller: Marks the device node as a gpio controller.
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H A Dgpio-ts4800.txt1 * TS-4800 FPGA's GPIO controller bindings
4 - compatible: Must be "technologic,ts4800-gpio".
5 - #gpio-cells: Should be two. The first cell is the pin number.
6 - reg: Physical base address of the controller and length
7 of memory mapped region.
10 - ngpios: See "gpio.txt"
15 compatible = "technologic,ts4800-gpio";
18 gpio-controller;
19 #gpio-cells = <2>;
/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dts4800-ts.txt1 * TS-4800 Touchscreen bindings
4 - compatible: must be "technologic,ts4800-ts"
5 - reg: physical base address of the controller and length of memory mapped
6 region.
7 - syscon: phandle / integers array that points to the syscon node which
8 describes the FPGA's syscon registers.
9 - phandle to FPGA's syscon
10 - offset to the touchscreen register
11 - offset to the touchscreen enable bit
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dtechnologic,ts4800.txt1 TS-4800 FPGA interrupt controller
3 TS-4800 FPGA has an internal interrupt controller. When one of the
8 - compatible: should be "technologic,ts4800-irqc"
9 - interrupt-controller: identifies the node as an interrupt controller
10 - reg: physical base address of the controller and length of memory mapped
11 region
12 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
14 - interrupts: specifies the interrupt line in the interrupt-parent controller
/linux/drivers/bus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
114 cores. This bus is for per-CPU tightly coupled devices such as the
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/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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