Searched +full:fpga +full:- +full:bridges (Results 1 – 5 of 5) sorted by relevance
1 FPGA Region Device Tree Binding6 - Introduction7 - Terminology8 - Sequence9 - FPGA Region10 - Supported Use Models11 - Device Tree Examples12 - Constraints18 FPGA Region[all...]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: FPGA Region10 - Michal Simek <michal.simek@amd.com>14 - Introduction15 - Terminology16 - Sequence17 - FPGA Region[all …]
4 decouplers / fpga bridges.5 The controller can decouple/disable the bridges which prevents signal7 couple / enable the bridges which allows traffic to pass through the11 Softcore is compatible with the Xilinx LogiCORE pr-decoupler.15 and AXI4-Lite interfaces on a Reconfigurable Partition when it is24 - compatible : Should contain "xlnx,pr-decoupler-1.00" followed by25 "xlnx,pr-decoupler" or26 "xlnx,dfx-axi-shutdown-manager-1.00" followed by27 "xlnx,dfx-axi-shutdown-manager"28 - regs : base address and size for decoupler module[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/fpga/xln[all...]
3 The Altera Freeze Bridge Controller manages one or more freeze bridges.4 The controller can freeze/disable the bridges which prevents signal6 unfreeze/enable the bridges which allows traffic to pass through the10 - compatible : Should contain "altr,freeze-bridge-controller"11 - regs : base address and size for freeze bridge module13 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.16 freeze-controller@100000450 {17 compatible = "altr,freeze-bridge-controller";19 bridge-enable = <0>;