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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dimx219.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
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H A Dthine,thp7312.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Elder <paul.elder@@ideasonboard.com>
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
23 - $ref: /schemas/media/video-interface-devices.yaml#
36 thine,boot-mode:
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
46 reset-gpios:
52 vddcore-supply:
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H A Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
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H A Dov8856.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sakar
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H A Disil,isl79987.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intersil ISL79987 Analog to MIPI CSI-2 decoder
10 - Michael Tretter <m.tretter@pengutronix.de>
11 - Marek Vasut <marex@denx.de>
14 The Intersil ISL79987 is an analog to MIPI CSI-2 decoder which is capable of
15 receiving up to four analog stream and multiplexing them into up to four MIPI
16 CSI-2 virtual channels, using one MIPI clock lane and 1/2 data lanes.
21 - isil,isl79987
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/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Duncore-other.json11 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
23 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
313 …"PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory c…
318 "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
324 …"PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CH…
335 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
352 "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
363 "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
374 "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
1046 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
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/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
18 3.24Gbit/sec per lane.
28 powerdown-gpios:
32 reset-gpios:
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H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
15 up to four data lanes.
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25 - renesas,r9a07g054-mipi-dsi # RZ/V2L
26 - const: renesas,rzg2l-mipi-dsi
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
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H A Dxlnx,zynqmp-psgtr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
18 "#phy-cells":
23 - description: The GTR lane
26 - description: The PHY type
28 - PHY_TYPE_DP
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
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H A Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
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H A Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td1 //=- AArch64SchedNeoverseN2.td - NeoverseN2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 10; // Micro-ops dispatched at a time.
15 let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer.
18 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
25 //===----------------------------------------------------------------------===//
27 // Instructions are first fetched and then decoded into internal macro-ops
29 // stages. A MOP can be split into two micro-ops further down the pipeline
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H A DAArch64SchedNeoverseV2.td1 //=- AArch64SchedNeoverseV2.td - NeoverseV2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2
14 //===----------------------------------------------------------------------===//
17 let IssueWidth = 16; // Micro-ops dispatched at a time.
18 let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
21 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
29 //===----------------------------------------------------------------------===//
31 // Instructions are first fetched and then decoded into internal macro-ops
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H A DAArch64SchedNeoverseV1.td1 //=- AArch64SchedNeoverseV1.td - NeoverseV1 Scheduling Model -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // - "Arm Neoverse V1 Software Optimization Guide"
13 // - "Arm Neoverse V1 Platform: Unleashing a new performance tier for Arm-based computing"
14 …//community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/neoverse-v1-plat…
15 // - "Neoverse V1"
19 //===----------------------------------------------------------------------===//
22 let IssueWidth = 15; // Maximum micro-ops dispatch rate.
23 let MicroOpBufferSize = 256; // Micro-op re-order buffer.
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H A DAArch64PerfectShuffle.h1 //===-- AArch64PerfectShuffle.h - AdvSIMD Perfect Shuffle Table -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file, which was autogenerated by llvm-PerfectShuffle, contains data
12 //===----------------------------------------------------------------------===//
29 2080972802U, // <0,0,0,1>: Cost 2 ins <0,0,u,1>, lane 2
31 2085707777U, // <0,0,0,3>: Cost 2 ins <0,u,0,3>, lane 1
33 2080440323U, // <0,0,0,5>: Cost 2 ins <0,0,0,u>, lane 3
34 2080440323U, // <0,0,0,6>: Cost 2 ins <0,0,0,u>, lane 3
35 2080440323U, // <0,0,0,7>: Cost 2 ins <0,0,0,u>, lane 3
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H A DAArch64SchedFalkorDetails.td1 //==- AArch64SchedFalkorDetails.td - Falkor Scheduling Defs -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exceptio
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-synology-ds414.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-binding
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/freebsd/sys/dev/drm2/
H A Ddrm_dp_helper.h120 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
123 * four bytes wide, starting with the one byte from the base info. As of
331 int lane);
333 int lane);
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific Operands.
16 //===----------------------------------------------------------------------===//
149 // Register list of four sequential D registers.
235 // Register list of four D registers, with "all lanes" subscripting.
244 // Register list of four D registers spaced by 2 (four sequential Q regs).
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H A DARMScheduleSwift.td1 //=- ARMScheduleSwift.td - Swift Scheduling Definitions -*- tablegen -*----===//
5 // SPDX-Licens
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H A DARMISelLowering.h1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
71 CALL_NOLINK, // Function call with branch not branch-and-link.
72 tSECALL, // CMSE non-secure function call.
76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
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/freebsd/contrib/libpcap/
H A Dpcap-filter.manmisc.in21 .TH PCAP-FILTER @MAN_MISC_INFO@ "13 June 2023"
23 pcap-filter \- packet filter syntax
54 E.g., `\fBhost\fP foo', `\fBnet\fP 128.3', `\fBport\fP 20', `\fBportrange\fP 6000-6008'.
75 E.g., `\fBsrc\fP foo', `\fBdst net\fP 128.3', `\fBsrc or dst port\fP ftp-data'.
106 `\fBudp portrange\fP 7000-7009', `\fBwlan addr2\fP 0:2:3:4:5:6'.
117 network interface''. FDDI headers contain Ethernet-like source
118 and destination addresses, and often contain Ethernet-like packet
146 E.g., `\fBhost\fP foo \fBand not port\fP ftp \fBand not port\fP ftp-data'.
149 `\fBtcp dst port\fP ftp \fBor\fP ftp-data \fBor\fP domain' is exactly the same as
150 `\fBtcp dst port\fP ftp \fBor tcp dst port\fP ftp-data \fBor tcp dst port\fP domain'.
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon_incl.td1 //===--- arm_neon_incl.td - ARM NEON compiler interface -------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
31 // A shorter version of Operation - takes a list of DAGs. The last of these will
37 foreach Index = 0-63 in
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
50 // op - Binary or unary operator, depending on the number of arguments. The
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