| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | cl_common_defines.h | 4 // the NVPTX back-end.
8 // Channel order
36 CLK_SNORM_INT8 = 0x10D0, // four channel RGBA unorm8
37 CLK_SNORM_INT16 = 0x10D1, // four channel RGBA unorm16
38 CLK_UNORM_INT8 = 0x10D2, // four channel RGBA unorm8
39 CLK_UNORM_INT16 = 0x10D3, // four channel RGBA unorm16
40 CLK_HALF_FLOAT = 0x10DD, // four channel RGBA half
41 CLK_FLOAT = 0x10DE, // four channel RGBA float
58 __CLK_UNORM_INT8888, // four channel ARGB unorm8
59 __CLK_UNORM_INT8888R, // four channel BGRA unorm8
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| /freebsd/sys/contrib/device-tree/Bindings/display/imx/ |
| H A D | ldb.txt | 1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
14 multiplexer in the front to select any of the four IPU display
15 interfaces as input for each LVDS channel.
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | snps-dma.txt | 4 - compatible: "snps,dma-spear1340"
5 - reg: Address range of the DMAC registers
6 - interrupt: Should contain the DMAC interrupt number
7 - dma-channels: Number of channels supported by hardware
8 - dma-requests: Number of DMA request lines supported, up to 16
9 - dma-masters: Number of AHB masters supported by the controller
10 - #dma-cells: must be <3>
11 - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
13 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
14 increase from chan n->0
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|
| H A D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
15 1. The channel id
17 3. A 32bit mask specifying the DMA channel configuration which are device
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/iio/addac/ |
| H A D | adi,ad74413r.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74412R and AD74413R are quad-channel software configurable input/output
18 The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
19 four configurable input/output channels and a suite of diagnostic functions.
20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
27 - adi,ad74412r
28 - adi,ad74413r
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|
| /freebsd/sys/contrib/device-tree/Bindings/dma/stm32/ |
| H A D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
15 1. The channel id
17 3. A 32bit mask specifying the DMA channel configuration which are device
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | imx.txt | 5 ---------------------------
12 - compatible : "fsl,imx-capture-subsystem";
13 - ports : Should contain a list of phandles pointing to camera
18 capture-subsystem {
19 compatible = "fsl,imx-capture-subsystem";
25 --------------
27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
29 combined with a D-PHY core mixed into the same register block. In
30 addition this device consists of an i.MX-specific "CSI2IPU gasket"
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | renesas,gyroadc.txt | 1 * Renesas R-Car GyroADC device driver
5 are sampled by the GyroADC block in a round-robin fashion and the result
9 - compatible: Should be "<soc-specific>", "renesas,rcar-gyroadc".
10 The <soc-specific> should be one of:
11 renesas,r8a7791-gyroadc - for the GyroADC block present
13 renesas,r8a7792-gyroadc - for the GyroADC with interrupt
15 - reg: Address and length of the register set for the device
16 - clocks: References to all the clocks specified in the clock-names
18 Documentation/devicetree/bindings/clock/clock-bindings.txt.
19 - clock-names: Shall contain "fck". The "fck" is the GyroADC block clock.
[all …]
|
| H A D | renesas,rcar-gyroadc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rcar-gyroadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car GyroADC
10 - Marek Vasut <marek.vasut+renesas@gmail.com>
15 are sampled by the GyroADC block in a round-robin fashion and the result
23 - enum:
24 - renesas,r8a7791-gyroadc
25 - renesas,r8a7792-gyroadc
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|
| /freebsd/sys/contrib/device-tree/Bindings/leds/ |
| H A D | leds-lm36274.txt | 1 * Texas Instruments LM36274 4-Channel LCD Backlight Driver w/Integrated Bias
3 The LM36274 is an integrated four-channel WLED driver and LCD bias supply.
4 The backlight boost provides the power to bias four parallel LED strings with
5 up to 29V total output voltage. The 11-bit LED current is programmable via
9 Documentation/devicetree/bindings/mfd/ti-lmu.txt
12 Documentation/devicetree/bindings/regulator/lm363x-regulator.txt
15 - compatible:
16 "ti,lm36274-backlight"
17 - reg : 0
18 - #address-cells : 1
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|
| /freebsd/sys/contrib/device-tree/Bindings/leds/backlight/ |
| H A D | richtek,rt4831-backlight.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/richtek,rt4831-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 For the LCD backlight, it can provide four channel WLED driving capability.
17 Each channel driving current is up to 30mA
20 https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
23 - $ref: common.yaml#
27 const: richtek,rt4831-backlight
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|
| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | dsi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
24 can control one to four virtual channels to one panel. Each virtual
25 channel should have a node "panel" for their virtual channel with their
26 reg-property set to the virtual channel number, usually there is just
27 one virtual channel, number 0.
33 clock-master:
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|
| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | brcm,bcm2835-system-timer.txt | 3 The System Timer peripheral provides four 32-bit timer channels and a
4 single 64-bit free running counter. Each channel has an output compare
10 - compatible : should be "brcm,bcm2835-system-timer"
11 - reg : Specifies base physical address and size of the registers.
12 - interrupts : A list of 4 interrupt sinks; one per timer channel.
13 - clock-frequency : The frequency of the clock that drives the counter, in Hz.
18 compatible = "brcm,bcm2835-system-timer";
21 clock-frequency = <1000000>;
|
| /freebsd/sys/contrib/device-tree/Bindings/iio/potentiometer/ |
| H A D | renesas,x9250.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
13 The Renesas X9250 integrates four digitally controlled potentiometers.
18 - $ref: /schemas/spi/spi-peripheral-props.yaml
23 - renesas,x9250t
24 - renesas,x9250u
29 vcc-supply:
33 avp-supply:
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|
| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | renesas,idt821034.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
13 The IDT821034 codec is a four channel PCM codec with onchip filters and
16 The time-slots used by the codec must be set and so, the properties
17 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
18 'dai-tdm-slot-rx-mask' must be present in the ALSA sound card node for
19 sub-nodes that involve the codec. The codec uses one 8bit time-slot per
20 channel.
[all …]
|
| H A D | ti,pcm6240.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022 - 2024 Texas Instruments Incorporated
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Shenghao Ding <shenghao-ding@ti.com>
24 https://www.ti.com/lit/gpn/pcm3120-q1
25 https://www.ti.com/lit/gpn/pcm3140-q1
26 https://www.ti.com/lit/gpn/pcm5120-q1
27 https://www.ti.com/lit/gpn/pcm6120-q1
28 https://www.ti.com/lit/gpn/pcm6260-q1
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|
| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | fsl,imx8qm-lvds-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 It converts two groups of four 7/10 bits of CMOS data into two
15 groups of four data lanes of LVDS data streams. A phase-locked
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
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|
| /freebsd/sys/isa/ |
| H A D | pnpreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
69 registers to their power-up values.
83 This register is write-only. The values are not sticky, that is,
94 pointer to the byte-serial device is reset. This register is
126 device, this location should be a read-only value of 0x00.
129 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
130 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
159 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | richtek,rt4831.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
19 For the LCD backlight, it can provide four channel WLED driving capability.
20 Each channel driving current is up to 30mA
23 https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
33 enable-gpios:
40 $ref: /schemas/regulator/richtek,rt4831-regulator.yaml
43 $ref: /schemas/leds/backlight/richtek,rt4831-backlight.yaml
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|
| /freebsd/share/man/man4/ |
| H A D | ads111x.4 | 35 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
60 .Va dev.ads111x.<unit>.<channel>.voltage
61 variable is accessed for a given channel, the driver switches the
62 chip's internal mux to choose the right input pins for that channel,
75 making either single-ended or differential measurements.
76 There are eight possible ways to combine the inputs from the four pins.
79 driver models that by creating a separate output channel for each of
82 the voltage variable for the channel number that corresponds the mux
86 When there is no channel config data, it creates all eight possible
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|
| H A D | ng_lmi.4 | 1 .\" Copyright (c) 1996-1999 Whistle Communications, Inc.
19 .\" MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
50 the ITU Annex A, ANSI Annex D, and Group-of-four LMI types.
51 It also supports auto-detection of the LMI type.
61 Typically, Annex A and Annex D live on DLCI 0 while Group-of-four
64 To enable LMI type auto-detection, connect the
72 Only one fixed LMI type, or auto-detection, can be active at any given time.
77 of the LMI protocol and each DLCI channel.
83 .Bl -tag -width ".Va auto1023"
89 Group-of-four LMI hook.
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|
| /freebsd/stand/common/ |
| H A D | isapnp.h | 16 * 4. Neither the name of the author nor the names of any co-contributors
70 registers to their power-up values.
84 This register is write-only. The values are not sticky, that is,
95 pointer to the byte-serial device is reset. This register is
127 device, this location should be a read-only value of 0x00.
130 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
131 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
158 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
159 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
163 Four memory resource registers per range, four ranges.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | fsl,cpm1-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
|
| H A D | fsl,qe-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
|
| /freebsd/contrib/ntp/libntp/lib/isc/include/isc/ |
| H A D | log.h | 2 * Copyright (C) 2004-2007, 2009 Internet Systems Consortium, Inc. ("ISC")
3 * Copyright (C) 1999-2002 Internet Software Consortium.
45 #define ISC_LOG_INFO (-1)
46 #define ISC_LOG_NOTICE (-2)
47 #define ISC_LOG_WARNING (-3)
48 #define ISC_LOG_ERROR (-4)
49 #define ISC_LOG_CRITICAL (-5)
64 * Channel flags.
84 #define ISC_LOG_ROLLINFINITE (-1)
85 #define ISC_LOG_ROLLNEVER (-2)
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|