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/linux/arch/arm/mach-tegra/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
26 #include <asm/mach-types.h>
48 * the flow controller state is cleared (which will cause the in tegra20_boot_secondary()
49 * flow controller to stop driving reset if the CPU has been in tegra20_boot_secondary()
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
57 * Unhalt the CPU. If the flow controller was used to in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
65 flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ in tegra20_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
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/linux/Documentation/hwmon/
H A Daquacomputer_d5next.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver aquacomputer-d5next
10 * Aquacomputer Farbwerk RGB controller
11 * Aquacomputer Farbwerk 360 RGB controller
12 * Aquacomputer Octo fan controller
13 * Aquacomputer Quadro fan controller
14 * Aquacomputer High Flow Next sensor
18 * Aquacomputer Poweradjust 3 fan controller
19 * Aquacomputer High Flow USB flow meter
20 * Aquacomputer MPS Flow devices
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/linux/drivers/hid/intel-thc-hid/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
8 tristate "Intel Touch Host Controller"
12 THC (Touch Host Controller) is the name of the IP block in PCH that
14 is comprised of 3 key functional blocks: A natively half-duplex
22 tristate "Intel QuickSPI driver based on Intel Touch Host Controller"
25 Intel QuickSPI, based on Touch Host Controller (THC), implements
28 transaction flow.
33 tristate "Intel QuickI2C driver based on Intel Touch Host Controller"
36 Intel QuickI2C, uses Touch Host Controller (THC) hardware, implements
39 transaction flow.
/linux/Documentation/devicetree/bindings/net/nfc/
H A Dmarvell,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell International Ltd. NCI NFC controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - marvell,nfc-i2c
16 - marvell,nfc-spi
17 - marvell,nfc-uart
19 hci-muxed:
30 reset-n-io:
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/linux/Documentation/gpu/
H A Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
23 -----
30 ------
39 -------------------
47 --------------------------
52 -----------------------------
56 Timing controller (timing_ctrlr)
57 --------------------------------
58 Final stage of display pipeline, Timing controller is not for the pixel
62 ------
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dcirrus,ep7209-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/cirrus,ep7209-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic CLPS711X Interrupt Controller
10 - Alexander Shiyan <shc_work@mail.ru>
13 Cirrus Logic CLPS711X Interrupt Controller
17 ---------------------------
24 8: TC1OI TC1 under flow
25 9: TC2OI TC2 under flow
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/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dfm10k.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for Intel(R) Ethernet Multi-host Controller
8 Copyright(c) 2015-2018 Intel Corporation.
12 - Identifying Your Adapter
13 - Additional Configurations
14 - Performance Tuning
15 - Known Issues
16 - Support
21 Ethernet Multi-host Controller.
28 Flow Control
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H A Dixgbe.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Known Issues
17 - Support
23 * Intel(R) Ethernet Controller 82598
24 * Intel(R) Ethernet Controller 82599
25 * Intel(R) Ethernet Controller X520
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/linux/drivers/net/mctp/
H A Dmctp-i2c.c1 // SPDX-License-Identifier: GPL-2.0
3 * Management Controller Transport Protocol (MCTP)
11 * shared between all mux I2C busses underneath. For non-mux cases an I2C client
14 * mctp-i2c-controller.yml devicetree binding has further details.
23 #include <linux/i2c-mux.h>
31 #define MCTP_I2C_MAXMTU (MCTP_I2C_MAXBLOCK - 1)
41 #define MCTP_I2C_OF_PROP "mctp-controller"
118 return i2c_root_adapter(&adap->dev); in mux_root_adapter()
120 /* In non-mux config all i2c adapters are root adapters */ in mux_root_adapter()
135 if (client->flags & I2C_CLIENT_TEN) { in mctp_i2c_new_client()
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/linux/drivers/char/tpm/
H A Dtpm_tis_spi_main.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Christophe Ricard <christophe-h.ricard@st.com>
10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
43 * TCG SPI flow control is documented in section 6.4 of the spec[1]. In short,
47 * [1] https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
55 if ((phy->iobuf[3] & 0x01) == 0) { in tpm_tis_spi_flow_control()
58 spi_xfer->len = 1; in tpm_tis_spi_flow_control()
61 ret = spi_sync_locked(phy->spi_device, &m); in tpm_tis_spi_flow_control()
64 if (phy->iobuf[0] & 0x01) in tpm_tis_spi_flow_control()
69 return -ETIMEDOUT; in tpm_tis_spi_flow_control()
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/linux/Documentation/core-api/
H A Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
15 handle all the different types of interrupt controller hardware. Device
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
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/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-flowctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-flowctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Flow Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-flowctrl
18 - nvidia,tegra30-flowctrl
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/linux/include/linux/hsi/
H A Dhsi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
31 HSI_FLOW_SYNC, /* Synchronized flow */
32 HSI_FLOW_PIPE, /* Pipelined flow */
36 HSI_ARB_RR, /* Round-robin arbitration */
58 * struct hsi_channel - channel resource used by the hsi clients
68 * struct hsi_config - Configuration for RX/TX HSI modules
74 * @flow: RX flow type (SYNCHRONIZED or PIPELINE)
84 unsigned int flow; /* RX only */ member
90 * struct hsi_board_info - HSI client board info
92 * @hsi_id: HSI controller id where the client sits
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/linux/Documentation/devicetree/bindings/crypto/
H A Damlogic,gxl-crypto.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/amlogic,gxl-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Corentin Labbe <clabbe@baylibre.com>
15 - const: amlogic,gxl-crypto
22 - description: Interrupt for flow 0
23 - description: Interrupt for flow 1
28 clock-names:
32 - compatible
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/linux/Documentation/devicetree/bindings/serial/
H A Dsocionext,milbeaut-usio-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/socionext,milbeaut-usio-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext Milbeaut UART controller
10 - Sugaya Taichi <sugaya.taichi@socionext.com>
13 - $ref: /schemas/serial/serial.yaml#
17 const: socionext,milbeaut-usio-uart
24 - description: RX interrupt specifier
25 - description: TX interrupt specifier
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H A Dsocionext,uniphier-uart.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier UART controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 const: socionext,uniphier-uart
28 auto-flow-control:
29 description: enable automatic flow control support.
33 - compatible
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/linux/Documentation/devicetree/bindings/hsi/
H A Dclient-devices.txt7 - hsi-channel-ids: A list of channel ids
9 - hsi-rx-mode: Receiver Bit transmission mode ("stream" or "frame")
10 - hsi-tx-mode: Transmitter Bit transmission mode ("stream" or "frame")
11 - hsi-mode: May be used instead hsi-rx-mode and hsi-tx-mode if
14 - hsi-speed-kbps: Max bit transmission speed in kbit/s
15 - hsi-flow: RX flow type ("synchronized" or "pipeline")
16 - hsi-arb-mode: Arbitration mode for TX frame ("round-robin", "priority")
20 - hsi-channel-names: A list with one name per channel specified in the
21 hsi-channel-ids property
26 hsi-controller {
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/linux/drivers/usb/dwc3/
H A Ddrd.c1 // SPDX-License-Identifier: GPL-2.0
3 * drd.c - DesignWare USB3 DRD Controller Dual-role support
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com
21 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); in dwc3_otg_disable_events()
24 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_disable_events()
29 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); in dwc3_otg_enable_events()
32 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_enable_events()
37 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVT); in dwc3_otg_clear_events()
39 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_clear_events()
56 spin_lock(&dwc->lock); in dwc3_otg_thread_irq()
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/linux/Documentation/hid/
H A Dintel-thc-hid.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Intel Touch Host Controller (THC)
7 Touch Host Controller is the name of the IP block in PCH that interface with Touch Devices (ex:
10 - A natively half-duplex Quad I/O capable SPI master
11 - Low latency I2C interface to support HIDI2C compliant devices
12 - A HW sequencer with RW DMA capability to system memory
29 -------------------------------
31 Below diagram illustrates the high-level architecture of THC software/hardware stack, which is fully
36 ----------------------------------------------
37 | +-----------------------------------+ |
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/linux/drivers/slimbus/
H A Dslimbus.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2011-2017, The Linux Foundation
79 /* Indicate that the frequency of the flow and the bus frequency are locked */
91 * struct slim_framer - Represents SLIMbus framer.
92 * Every controller may have multiple framers. There is 1 active framer device
94 * Manager is responsible for framer hand-over.
111 * struct slim_msg_txn - Message to be sent by the controller.
120 * (relevant for message-codes involving read operation)
152 * enum slim_clk_state: SLIMbus controller's clock state used internally for
158 * @SLIM_CLK_PAUSED: SLIMbus controller clock has paused.
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/linux/drivers/net/ethernet/ti/
H A Dcpsw_sl.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
33 CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */
34 CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */
47 CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */
48 CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */
/linux/drivers/hsi/
H A Dhsi_core.c1 // SPDX-License-Identifier: GPL-2.0-only
45 if (strcmp(dev_name(dev), driver->name) == 0) in hsi_bus_match()
62 kfree(cl->tx_cfg.channels); in hsi_client_release()
63 kfree(cl->rx_cfg.channels); in hsi_client_release()
77 cl->tx_cfg = info->tx_cfg; in hsi_new_client()
78 if (cl->tx_cfg.channels) { in hsi_new_client()
79 size = cl->tx_cfg.num_channels * sizeof(*cl->tx_cfg.channels); in hsi_new_client()
80 cl->tx_cfg.channels = kmemdup(info->tx_cfg.channels, size, in hsi_new_client()
82 if (!cl->tx_cfg.channels) in hsi_new_client()
86 cl->rx_cfg = info->rx_cfg; in hsi_new_client()
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/linux/drivers/soc/tegra/
H A Dflowctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
46 /* ensure the update has reached the flow controller */ in flowctrl_update()
99 * power-gating (like memory running off PLLP), in flowctrl_cpu_suspend_enter()
103 * while wfe for the power-gating, just like it in flowctrl_cpu_suspend_enter()
132 /* Disable powergating via flow controller for CPU0 */ in flowctrl_cpu_suspend_exit()
170 { .compatible = "nvidia,tegra210-flowctrl" },
171 { .compatible = "nvidia,tegra124-flowctrl" },
172 { .compatible = "nvidia,tegra114-flowctrl" },
173 { .compatible = "nvidia,tegra30-flowctrl" },
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/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_cls.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * RSS and Classifier definitions for Marvell PPv2 Network Controller
22 /* Classifier flow constants */
143 /* Number of per-port dedicated entries in the C2 TCAM */
146 /* Each port has one range per flow type + one entry controlling the global RSS
151 #define MVPP22_CLS_C2_RSS_ENTRY(p) (MVPP22_CLS_C2_PORT_FIRST((p) + 1) - 1)
157 /* Packet flow ID */
176 MVPP2_FL_IP4_UNTAG, /* non-TCP, non-UDP, same for below */
185 /* LU Type defined for all engines, and specified in the flow table */
189 /* rule->loc is used as a lu-type for the entries 0 - 62. */
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/linux/net/sched/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 need a certain minimum data flow rate, or if you need to limit the
22 maximum data flow rate for traffic which matches specified criteria.
25 To administer these schedulers, you'll need the user-level utilities
54 in-depth articles.
74 Say Y here if you want to use an n-band priority queue packet
81 tristate "Hardware Multiqueue-aware Multi Band Queuing (MULTIQ)"
83 Say Y here if you want to use an n-band queue packet scheduler
199 re-ordering. This is often useful to simulate networks when
219 tristate "Multi-queue priority scheduler (MQPRIO)"
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