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/linux/drivers/input/touchscreen/
H A Dbu21013_ts.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
4 * Author: Naveen Kumar G <naveen.gaddipati@stericsson.com> for ST-Ericsson
140 * struct bu21013_ts - touch panel data structure
145 * @cs_gpiod: chip select GPIO line
176 ret = i2c_smbus_read_i2c_block_data(ts->client, in bu21013_read_block_data()
183 return -EINVAL; in bu21013_read_block_data()
188 struct input_dev *input = ts->in_dev; in bu21013_do_touch_report()
197 return -EINVAL; in bu21013_do_touch_report()
213 &ts->props, x, y); in bu21013_do_touch_report()
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/linux/drivers/sbus/char/
H A Ddisplay7seg.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* display7seg.c - Driver implementation for the 7-segment display
32 /* Solaris compatibility flag -
34 * documented driver features (ref Sun doc 806-0180-03).
38 * 1) Device ALWAYS reverts to OBP-specified FLIPPED mode
41 * FLIP bit
44 * omitting above features, set this parameter to non-zero.
51 MODULE_DESCRIPTION("7-Segment Display driver for Sun Microsystems CP1400/1500");
61 * Register block address- see header for details
62 * -----------------------------------------
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/linux/drivers/ata/
H A Dpata_sl82c105.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sl82c105.c - SL82C105 PATA for new ATA layer
14 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
45 * sl82c105_pre_reset - probe begin
58 struct ata_port *ap = link->ap; in sl82c105_pre_reset()
59 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in sl82c105_pre_reset()
61 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) in sl82c105_pre_reset()
62 return -ENOENT; in sl82c105_pre_reset()
68 * sl82c105_configure_piomode - set chip PIO timing
80 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in sl82c105_configure_piomode()
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H A Dpata_mpiix.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_mpiix.c - Intel MPIIX PATA for new ATA layer
4 * (C) 2005-2006 Red Hat Inc
12 * devices. The chip is a bridge (pardon the pun) between the old world of
14 * IDE controller is not decoded in PCI space and the chip does not claim to
15 * be IDE class PCI. This requires slightly non-standard probe logic compared
51 struct ata_port *ap = link->ap; in mpiix_pre_reset()
52 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in mpiix_pre_reset()
56 return -ENOENT; in mpiix_pre_reset()
62 * mpiix_set_piomode - set initial PIO mode data
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H A Dpata_ns87415.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_ns87415.c - NS87415 (and PARISC SUPERIO 87560) PATA
11 * This driver assumes the firmware has left the chip in a valid ST506
39 * ns87415_set_mode - Initialize host controller mode timings
45 * device. Because the chip is quite an old design we have to do this
54 struct pci_dev *dev = to_pci_dev(ap->host->dev); in ns87415_set_mode()
55 int unit = 2 * ap->port_no + adev->devno; in ns87415_set_mode()
63 /* Timing register format is 17 - low nybble read timing with in ns87415_set_mode()
64 the high nybble being 16 - x for recovery time in PCI clocks */ in ns87415_set_mode()
66 ata_timing_compute(adev, adev->pio_mode, &t, T, 0); in ns87415_set_mode()
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H A Dpata_pdc202xx_old.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc2026x_cable_detect()
33 if (cis & (1 << (10 + ap->port_no))) in pdc2026x_cable_detect()
41 iowrite8(tf->command, ap->ioaddr.command_addr); in pdc202xx_exec_command()
47 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_irq_check()
51 if (ap->port_no) { in pdc202xx_irq_check()
67 * pdc202xx_configure_piomode - set chip PIO timing
79 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_configure_piomode()
80 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; in pdc202xx_configure_piomode()
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/linux/drivers/media/dvb-frontends/
H A Dlgdt330x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Support for LGDT3302 and LGDT3303 - VSB/QAM
20 * struct lgdt330x_config - contains lgdt330x configuration
22 * @demod_chip: LG demodulator chip LGDT3302 or LGDT3303
23 * @serial_mpeg: MPEG hardware interface - 0:parallel 1:serial
27 * Flip the polarity of the mpeg data transfer clock using alternate
29 * This option applies ONLY to LGDT3303 - 0:disabled (default) 1:enabled
/linux/include/linux/
H A Drmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011-2016 Synaptics Incorporated
21 * struct rmi_2d_axis_alignment - target axis alignment
22 * @swap_axes: set to TRUE if desired to swap x- and y-axis
23 * @flip_x: set to TRUE if desired to flip direction on x-axis
24 * @flip_y: set to TRUE if desired to flip direction on y-axis
25 * @clip_x_low - reported X coordinates below this setting will be clipped to
27 * @clip_x_high - reported X coordinates above this setting will be clipped to
29 * @clip_y_low - reported Y coordinates below this setting will be clipped to
31 * @clip_y_high - reported Y coordinates above this setting will be clipped to
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/linux/arch/alpha/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-alpha/dma.h
6 * use ISA-compatible dma. The only extension is support for high-page
7 * registers that allow to set the top 8 bits of a 32-bit DMA address.
31 * controller 1: channels 0-3, byte operations, ports 00-1F
32 * controller 2: channels 4-7, word operations, ports C0-DF
34 * - ALL registers are 8 bits only, regardless of transfer size
35 * - channel 4 is not used - cascades 1 into 2.
36 * - channels 0-3 are byte - addresses/counts are for physical bytes
37 * - channels 5-7 are word - addresses/counts are for physical words
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/linux/drivers/irqchip/
H A Dirq-dw-apb-ictl.c38 for (n = 0; n < d->revmap_size; n += 32) { in dw_apb_ictl_handle_irq()
40 u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); in dw_apb_ictl_handle_irq()
43 u32 hwirq = ffs(stat) - 1; in dw_apb_ictl_handle_irq()
54 struct irq_chip *chip = irq_desc_get_chip(desc); in dw_apb_ictl_handle_irq_cascaded() local
57 chained_irq_enter(chip, desc); in dw_apb_ictl_handle_irq_cascaded()
59 for (n = 0; n < d->revmap_size; n += 32) { in dw_apb_ictl_handle_irq_cascaded()
61 u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); in dw_apb_ictl_handle_irq_cascaded()
64 u32 hwirq = ffs(stat) - 1; in dw_apb_ictl_handle_irq_cascaded()
65 generic_handle_domain_irq(d, gc->irq_base + hwirq); in dw_apb_ictl_handle_irq_cascaded()
71 chained_irq_exit(chip, desc); in dw_apb_ictl_handle_irq_cascaded()
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/linux/drivers/media/usb/gspca/gl860/
H A Dgl860.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* GSPCA subdrivers for Genesys Logic webcams with the GL860 chip
23 #define _MI1320_ (((struct sd *) gspca_dev)->sensor == ID_MI1320)
24 #define _MI2020_ (((struct sd *) gspca_dev)->sensor == ID_MI2020)
25 #define _OV2640_ (((struct sd *) gspca_dev)->sensor == ID_OV2640)
26 #define _OV9655_ (((struct sd *) gspca_dev)->sensor == ID_OV9655)
43 u8 flip; member
H A Dgl860-ov2640.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Subdriver for the GL860 chip with the OV2640 sensor
175 sd->vcur.backlight = 32; in ov2640_init_settings()
176 sd->vcur.brightness = 0; in ov2640_init_settings()
177 sd->vcur.sharpness = 6; in ov2640_init_settings()
178 sd->vcur.contrast = 0; in ov2640_init_settings()
179 sd->vcur.gamma = 32; in ov2640_init_settings()
180 sd->vcur.hue = 0; in ov2640_init_settings()
181 sd->vcur.saturation = 128; in ov2640_init_settings()
182 sd->vcur.whitebal = 64; in ov2640_init_settings()
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H A Dgl860-mi1320.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Subdriver for the GL860 chip with the MI1320 sensor
204 sd->vcur.backlight = 0; in mi1320_init_settings()
205 sd->vcur.brightness = 0; in mi1320_init_settings()
206 sd->vcur.sharpness = 6; in mi1320_init_settings()
207 sd->vcur.contrast = 10; in mi1320_init_settings()
208 sd->vcur.gamma = 20; in mi1320_init_settings()
209 sd->vcur.hue = 0; in mi1320_init_settings()
210 sd->vcur.saturation = 6; in mi1320_init_settings()
211 sd->vcur.whitebal = 0; in mi1320_init_settings()
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H A Dgl860-mi2020.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Subdriver for the GL860 chip with the MI2020 sensor
82 {2, {0xff, 0xff, 0xff}}, /* - */
355 sd->vcur.backlight = 0; in mi2020_init_settings()
356 sd->vcur.brightness = 70; in mi2020_init_settings()
357 sd->vcur.sharpness = 20; in mi2020_init_settings()
358 sd->vcur.contrast = 0; in mi2020_init_settings()
359 sd->vcur.gamma = 0; in mi2020_init_settings()
360 sd->vcur.hue = 0; in mi2020_init_settings()
361 sd->vcur.saturation = 60; in mi2020_init_settings()
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H A Dgl860.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* GSPCA subdrivers for Genesys Logic webcams with the GL860 chip
6 * GSPCA by Jean-Francois Moine <http://moinejf.free.fr>
52 container_of(ctrl->handler, struct gspca_dev, ctrl_handler); in sd_s_ctrl()
55 switch (ctrl->id) { in sd_s_ctrl()
57 sd->vcur.brightness = ctrl->val; in sd_s_ctrl()
60 sd->vcur.contrast = ctrl->val; in sd_s_ctrl()
63 sd->vcur.saturation = ctrl->val; in sd_s_ctrl()
66 sd->vcur.hue = ctrl->val; in sd_s_ctrl()
69 sd->vcur.gamma = ctrl->val; in sd_s_ctrl()
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/linux/drivers/media/usb/gspca/
H A Dstk1135.c1 // SPDX-License-Identifier: GPL-2.0-or-later
45 /* -- read a register -- */
48 struct usb_device *dev = gspca_dev->dev; in reg_r()
51 if (gspca_dev->usb_err < 0) in reg_r()
58 gspca_dev->usb_buf, 1, in reg_r()
62 index, gspca_dev->usb_buf[0]); in reg_r()
65 gspca_dev->usb_err = ret; in reg_r()
69 return gspca_dev->usb_buf[0]; in reg_r()
72 /* -- write a register -- */
76 struct usb_device *dev = gspca_dev->dev; in reg_w()
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/linux/sound/pci/
H A Dals300.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * als300.c - driver for Avance Logic ALS300/ALS300+ soundcards.
16 * This is why we always use 2 periods. We can then use a flip-flop variable
24 #include <linux/dma-mapping.h>
151 static void snd_als300_set_irq_flag(struct snd_als300 *chip, int cmd) in snd_als300_set_irq_flag() argument
153 u32 tmp = snd_als300_gcr_read(chip->port, MISC_CONTROL); in snd_als300_set_irq_flag()
158 if (((chip->revision > 5 || chip->chip_type == DEVICE_ALS300_PLUS) ^ in snd_als300_set_irq_flag()
163 snd_als300_gcr_write(chip->port, MISC_CONTROL, tmp); in snd_als300_set_irq_flag()
168 struct snd_als300 *chip = card->private_data; in snd_als300_free() local
170 snd_als300_set_irq_flag(chip, IRQ_DISABLE); in snd_als300_free()
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/linux/drivers/gpu/drm/panel/
H A Dpanel-raspberrypi-touchscreen.c2 * Copyright © 2016-2017 Broadcom
8 * Portions of this file (derived from panel-simple.c) are:
25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
36 * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR
47 #include <linux/media-bus-format.h>
58 #define RPI_DSI_DRIVER_NAME "rpi-ts-dsi"
63 REG_PORTA, /* BIT(2) for horizontal flip, BIT(3) for vertical flip */
83 /* DSI D-PHY Layer Registers */
161 /* DBI-B Host Registers */
184 /* Chip/Rev Registers */
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/linux/drivers/net/ethernet/cirrus/
H A Dcs89x0.h1 /* Copyright, 1988-1992, Russell Nelson, Crynwr Software
18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
19 /* offset 2h -> Model/Product Number */
20 /* offset 3h -> Chip Revision Number */
87 #define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
95 #define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */
131 /* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
142 /* PP_RxCTL - Receive Control bit definition - Read/write */
153 /* Default receive mode - individually addressed, broadcast, and error free */
156 /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
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/linux/arch/m68k/include/asm/
H A Dmac_via.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * via them as are assorted bits and bobs - eg rtc, adb. The picture
51 * is the bit to flip screen buffers.
59 * state-control line SEL" on all but IIfx
83 /* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
85 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
89 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
112 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
113 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
117 * correspond to a VIA work-alike named 'EVR'. */
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h3 * Copyright (c) 2007-2008 Intel Corporation
71 /* these are outputs from the chip - integrated only
89 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
105 * create the DMA scatter-gather list for each FB color plane. This sg
117 * in the rotated and remapped GTT view all no-CCS formats (up to 2
225 * state. This must be called _after_ display->get_pipe_config has
226 * pre-filled the pipe config. Note that intel_encoder->bas
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H A Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
144 return (crtc_state->active_planes & in is_hdr_mode()
180 return crtc_state->master_transcoder != INVALID_TRANSCODER; in is_trans_port_sync_slave()
186 return crtc_state->sync_mode_slaves_mask != 0; in is_trans_port_sync_master()
198 return ffs(crtc_state->joiner_pipes) - 1; in joiner_primary_pipe()
207 return hweight8(crtc_state->joiner_pipes) >= 2; in is_bigjoiner()
215 return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state)); in bigjoiner_primary_pipes()
223 return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state)); in bigjoiner_secondary_pipes()
228 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_is_bigjoiner_primary()
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/linux/drivers/gpu/drm/loongson/
H A Dlsdc_drv.h1 /* SPDX-License-Identifier: GPL-2.0+ */
31 * Loongson 3 series processors, they are equipped with on-board video RAM
48 lsdc_device_probe(struct pci_dev *pdev, enum loongson_chip_id chip);
112 void (*flip)(struct lsdc_crtc *lcrtc); member
348 return readl(ldev->reg_base + offset); in lsdc_rreg32()
353 writel(val, ldev->reg_base + offset); in lsdc_wreg32()
360 void __iomem *addr = ldev->reg_base + offset; in lsdc_ureg32_set()
370 void __iomem *addr = ldev->reg_base + offset; in lsdc_ureg32_clr()
379 return readl(ldev->reg_base + offset + pipe * CRTC_PIPE_OFFSET); in lsdc_pipe_rreg32()
385 writel(val, ldev->reg_base + offset + pipe * CRTC_PIPE_OFFSET); in lsdc_pipe_wreg32()
/linux/Documentation/devicetree/bindings/input/
H A Diqs62x-keys.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/iqs62x-keys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 - $ref: input.yaml#
16 The Azoteq IQS620A, IQS621, IQS622, IQS624 and IQS625 multi-function sensors
17 feature a variety of self-capacitive, mutual-inductive and Hall-effect sens-
23 further details and examples. Sensor hardware configuration (self-capacitive
24 vs. mutual-inductive, etc.) is selected based on the device's firmware.
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/linux/drivers/gpio/
H A Dgpio-omap.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
27 #include <linux/platform_data/gpio-omap.h>
61 struct gpio_chip chip; member
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
91 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); in omap_irq_data_get_bank() local
92 return gpiochip_get_data(chip); in omap_irq_data_get_bank()
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
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