Home
last modified time | relevance | path

Searched +full:flash +full:- +full:dma (Results 1 – 25 of 298) sorted by relevance

12345678910>>...12

/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dgpmi-nand.txt1 * Freescale General-Purpose Media Interface (GPMI)
4 NAND flash chips.
7 - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
13 - reg : should contain registers location and length for gpmi and bch.
14 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
15 - interrupts : BCH interrupt number.
16 - interrupt-names : Should be "bch".
17 - dmas: DMA specifier, consisting of a phandle to DMA controller node
18 and GPMI DMA channel ID.
19 Refer to dma.txt and fsl-mxs-dma.txt for details.
[all …]
H A Dbrcm,brcmnand.txt3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
26 brcm,brcmnand-v5.0
[all …]
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
17 is paired with a custom DMA engine (inventively named "Flash DMA") which
25 -- Additional SoC-specific NAND controller properties --
33 interesting ways, sometimes with registers that lump multiple NAND-related
[all …]
H A Dgpmi-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI)
10 - Han Xu <han.xu@nxp.com>
14 flash chips. The device tree may optionally contain sub-nodes
21 - enum:
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
[all …]
H A Dqcom_nandc.txt4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
6 SoC and it uses ADM DMA
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
8 IPQ4019 SoC and it uses BAM DMA
9 * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
10 IPQ6018 SoC and it uses BAM DMA
11 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
12 IPQ8074 SoC and it uses BAM DMA
13 * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
[all …]
H A Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
[all …]
H A Daspeed-smc.txt2 * Aspeed SPI Flash Memory Controller
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
20 - #address-cells : must be 1 corresponding to chip select child binding
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dcavium-compact-flash.txt1 * Compact Flash
3 The Cavium Compact Flash device is connected to the Octeon Boot Bus,
5 industry standard compact flash devices.
8 - compatible: "cavium,ebt3000-compact-flash";
12 - reg: The base address of the CF chip select banks. Depending on
15 - cavium,bus-width: The width of the connection to the CF devices. Valid
18 - cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
20 - cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
24 compact-flash@5,0 {
25 compatible = "cavium,ebt3000-compact-flash";
[all …]
H A Dpata-arasan.txt1 * ARASAN PATA COMPACT FLASH CONTROLLER
4 - compatible: "arasan,cf-spear1340"
5 - reg: Address range of the CF registers
6 - interrupt: Should contain the CF interrupt number
7 - clock-frequency: Interface clock rate, in Hz, one of
21 - arasan,broken-udma: if present, UDMA mode is unusable
22 - arasan,broken-mwdma: if present, MWDMA mode is unusable
23 - arasan,broken-pio: if present, PIO mode is unusable
24 - dmas: one DMA channel, as described in bindings/dma/dma.txt
26 - dma-names: the corresponding channel name, must be "data"
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc8610_hpcd.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <32768>; // L1
[all …]
H A Dxpedite5200.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dmpc8349emitx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8349E-mITX Device Tree Source
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <32768>;
[all …]
H A Dxpedite5200_xmon.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 * xMon boot loader memory map which differs from U-Boot's.
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 form-factor = "PMC/XMC";
18 boot-bank = <0x0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
39 d-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dtqm8560.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
[all …]
H A Dtqm8548-bigflash.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dtqm8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
34 d-cache-size = <0x8000>; // L1, 32K
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j7200-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200.dtsi"
18 reserved_memory: reserved-memory {
19 #address-cells = <2>;
20 #size-cell
[all...]
H A Dk3-j721e-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
20 reserved_memory: reserved-memory {
21 #address-cells = <2>;
22 #size-cell
[all...]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dintel,ixp4xx-expansion-bus-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15 - Linus Walleij <linus.walleij@linaro.org>
19 pattern: '^bus@[0-9a-f]+$'
23 - enum:
24 - intel,ixp42x-expansion-bus-controller
25 - intel,ixp43x-expansion-bus-controller
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Drockchip-sfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/rockchip-sf
[all...]
H A Damlogic,meson6-spifc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SPI Flash Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 - $ref: spi-controller.yaml#
18 NOR memories, without DMA support and a 64-byte unified transmit /
24 - amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
25 - amlogic,meson-gxbb-spifc # SPI Flash Controller on GXBB and compatible SoCs
[all …]

12345678910>>...12