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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260.dtsi116 clocks = <&fin_pll>,
120 clock-names = "fin_pll",
130 clocks = <&fin_pll>,
134 <&fin_pll>,
143 clock-names = "fin_pll",
162 clocks = <&fin_pll>,
164 clock-names = "fin_pll",
172 clocks = <&fin_pll>,
174 clock-names = "fin_pll",
182 clocks = <&fin_pll>,
[all …]
H A Ds3c6410-smdk6410.dts31 fin_pll: oscillator-0 { label
34 clock-output-names = "fin_pll";
65 clocks = <&fin_pll>;
H A Ds3c6410-mini6410.dts31 fin_pll: oscillator-0 { label
34 clock-output-names = "fin_pll";
161 clocks = <&fin_pll>;
H A Dexynos5260-xyref5260.dts30 fin_pll: xxti { label
33 clock-output-names = "fin_pll";
H A Dexynos5410-smdk5410.dts30 fin_pll: xxti { label
33 clock-output-names = "fin_pll";
H A Dexynos5410-odroidxu.dts51 fin_pll: xxti { label
54 clock-output-names = "fin_pll";
104 clocks = <&fin_pll>;
H A Dexynos4210.dtsi287 clock-names = "fin_pll", "mct";
H A Dexynos4x12.dtsi300 clock-names = "fin_pll", "mct";
H A Dexynos3250.dtsi456 clock-names = "fin_pll", "mct";
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5260-clock.yaml18 - "fin_pll" - PLL input clock from XXTI
96 - const: fin_pll
116 - const: fin_pll
145 - const: fin_pll
163 - const: fin_pll
181 - const: fin_pll
199 - const: fin_pll
216 - const: fin_pll
234 - const: fin_pll
251 - const: fin_pll
[all …]
H A Dsamsung,exynos7-clock.yaml18 - "fin_pll" - PLL input clock from XXTI
70 - const: fin_pll
92 - const: fin_pll
113 - const: fin_pll
131 - const: fin_pll
150 - const: fin_pll
179 - const: fin_pll
197 - const: fin_pll
216 - const: fin_pll
239 - const: fin_pll
[all …]
H A Dtesla,fsd-clock.yaml59 - const: fin_pll
76 - const: fin_pll
98 - const: fin_pll
120 - const: fin_pll
139 - const: fin_pll
155 - const: fin_pll
169 - const: fin_pll
190 clocks = <&fin_pll>,
193 clock-names = "fin_pll",
H A Daxis,artpec8-clock.yaml74 - const: fin_pll
91 - const: fin_pll
110 - const: fin_pll
128 - const: fin_pll
148 - const: fin_pll
169 - const: fin_pll
189 - const: fin_pll
205 clocks = <&fin_pll>,
210 clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
H A Dsamsung,exynos5410-clock.yaml18 - "fin_pll" - PLL input clock from XXTI
33 defined using standard clock bindings with "fin_pll" clock-output-name.
54 fin_pll: osc-clock {
57 clock-output-names = "fin_pll";
65 clocks = <&fin_pll>;
H A Dsamsung,s3c6400-clock.yaml16 - "fin_pll" - PLL input clock (xtal/extclk) - required,
56 clocks = <&fin_pll>;
H A Dsamsung,exynos-audss-clock.yaml31 Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
/linux/drivers/clk/samsung/
H A Dclk-fsd.c174 PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
176 PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
178 PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
180 PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
185 PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
186 PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
187 PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
188 PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
189 PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
190 PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
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H A Dclk-artpec8.c179 PLL(pll_1017x, CLK_FOUT_SHARED0_PLL, "fout_pll_shared0", "fin_pll",
181 PLL(pll_1017x, CLK_FOUT_SHARED1_PLL, "fout_pll_shared1", "fin_pll",
183 PLL(pll_1031x, CLK_FOUT_AUDIO_PLL, "fout_pll_audio", "fin_pll",
239 PNAME(mout_clkcmu_pll_shared0_p) = { "fin_pll", "fout_pll_shared0" };
240 PNAME(mout_clkcmu_pll_shared1_p) = { "fin_pll", "fout_pll_shared1" };
241 PNAME(mout_clkcmu_pll_audio_p) = { "fin_pll", "fout_pll_audio" };
244 FFACTOR(CLK_DOUT_CMU_OTP, "dout_clkcmu_otp", "fin_pll", 1, 8, 0),
388 PNAME(mout_clk_bus_aclk_user_p) = { "fin_pll", "dout_clkcmu_bus" };
389 PNAME(mout_clk_bus_dlp_user_p) = { "fin_pll", "dout_clkcmu_bus_dlp" };
424 PNAME(mout_clk_core_aclk_user_p) = { "fin_pll", "dout_clkcmu_core_main" };
[all …]
H A Dclk-exynos4.c283 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
284 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
285 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
286 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
287 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
339 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
357 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
358 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
359 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
1014 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi40 fin_pll: clock { label
43 clock-output-names = "fin_pll";
175 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
180 clock-names = "fin_pll", "dout_sclk_bus0_pll",
189 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
193 clock-names = "fin_pll", "dout_sclk_bus0_pll",
202 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
203 clock-names = "fin_pll", "dout_aclk_ccore_133";
210 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
212 clock-names = "fin_pll", "dout_aclk_peric0_66",
[all …]
H A Dexynos7-espresso.dts58 &fin_pll {
H A Dexynos850.dtsi188 clock-names = "fin_pll", "mct";
/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml48 - const: fin_pll
176 clock-names = "fin_pll", "mct";
196 clock-names = "fin_pll", "mct";
217 clock-names = "fin_pll", "mct";
237 clock-names = "fin_pll", "mct";
/linux/arch/arm64/boot/dts/tesla/
H A Dfsd-evb.dts87 &fin_pll {
/linux/include/dt-bindings/clock/
H A Ds5pv210.h13 #define FIN_PLL 1 macro

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