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/linux/drivers/gpu/drm/xe/
H A Dxe_hw_engine_group_types.h37 /** @resume_work: worker to resume faulting LR exec queues */
39 /** @resume_wq: workqueue to resume faulting LR exec queues */
43 * mutual exclusion between execution only in faulting LR mode and
/linux/tools/testing/selftests/powerpc/tm/
H A Dtm-signal-pagefault.c8 * In order to avoid pre-faulting the signal stack memory and to force the
14 * the same mechanism used to avoid pre-faulting the signal stack memory.
44 * Data that will be copied into the faulting pages (instead of zero-filled
57 * 'backing_mem' and then copied into the faulting pages when the page fault
71 /* Save the data that will be copied into the faulting page */ in get_uf_mem()
120 * So, round faulting address down to page boundary. in fault_handler_thread()
/linux/arch/hexagon/include/asm/
H A Duaccess.h16 * When a kernel-mode page fault is taken, the faulting instruction
20 * be resumed instead of the faulting instruction, so as to effect
/linux/arch/powerpc/kvm/
H A Dbook3s_rmhandlers.S81 /* Should we just skip the faulting instruction? */
108 * Bring us back to the faulting code, but skip the
109 * faulting instruction.
H A Dbook3s_64_entry.S127 * the faulting instruction in guest memory from the hypervisor without
135 * the faulting instruction using the faulting guest effective address.
/linux/Documentation/gpu/rfc/
H A Dgpusvm.rst17 fixing do_swap_page to lock the faulting page. A driver-exclusive lock
19 the faulting page.
21 migrate can actually migrate, with only the faulting page guaranteed
/linux/arch/alpha/include/asm/
H A Dextable.h8 * - insn is a 32-bit pc-relative offset from the faulting insn.
9 * - nextinsn is a 16-bit offset off of the faulting instruction
/linux/arch/powerpc/kernel/
H A Dhead_44x.S311 mfspr r10, SPRN_DEAR /* Get faulting address */
313 /* If we are faulting a kernel address, we have to use the
394 /* Re-load the faulting address */
425 mfspr r10, SPRN_SRR0 /* Get faulting address */
427 /* If we are faulting a kernel address, we have to use the
493 /* Re-load the faulting address */
528 * Create WS1. This is the faulting address (EPN),
565 mfspr r10,SPRN_DEAR /* Get faulting address */
567 /* If we are faulting a kernel address, we have to use the
666 mfspr r10,SPRN_SRR0 /* Get faulting address */
[all …]
/linux/arch/m68k/ifpsp060/
H A Dfskeleton.S110 | stack frame. The FP state frame holds the source operand of the faulting
129 | stack frame. The FP state frame holds the source operand of the faulting
148 | stack frame. The FP state frame holds the source operand of the faulting
167 | stack frame. The FP state frame holds the source operand of the faulting
/linux/arch/powerpc/mm/nohash/
H A Dtlb_low_64e.S59 mfspr r16,\addr /* get faulting address */
139 * r16 = faulting address
283 * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
513 * r16 = virtual page table faulting address
670 * r16 = faulting address
729 * restore to the initial faulting context, whatever it was.
/linux/Documentation/arch/x86/
H A Dmds.rst19 can also happen to a faulting or assisting load operation for a different
30 can then be forwarded to a faulting or assisting load operation, which can
38 faulting or assisting loads under certain conditions, which again can be
/linux/arch/sparc/include/asm/
H A Decc.h58 * MID: ModuleID of the faulting processor. ie. who did it?
60 * VA: Bits 19-12 of the virtual faulting address, these are the
/linux/Documentation/admin-guide/mm/
H A Duserfaultfd.rst167 decide what content to provide before the faulting thread continues.
173 faulting thread continue with ``UFFDIO_CONTINUE``.
189 those IOCTLs wakes up the faulting thread.
404 to zeromap the faulting address. However, in the latter case, when an
/linux/arch/arm64/include/asm/
H A Dinsn-def.h19 * Unlike kgdb, #imm16 value with unallocated handler is used for faulting.
/linux/arch/x86/mm/
H A Dmmio-mod.c72 MODULE_PARM_DESC(trace_pc, "Record address of faulting instructions.");
111 pr_emerg("faulting IP is at %pS\n", (void *)regs->ip); in die_kmmio_nesting_error()
112 pr_emerg("last faulting IP was at %pS\n", (void *)my_reason->ip); in die_kmmio_nesting_error()
/linux/virt/kvm/
H A Dasync_pf.c74 * Notify and kick the vCPU even if faulting in the page failed, e.g. in async_pf_execute()
193 * may as well sleep faulting in page in kvm_setup_async_pf()
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dintroduction.rst105 0x7 出錯(Faulting)虛擬地址 BADV
106 0x8 出錯(Faulting)指令字 BADI
134 0x89 TLB重填異常出錯(Faulting)虛地址 TLBRBADV
/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dintroduction.rst105 0x7 出错(Faulting)虚拟地址 BADV
106 0x8 出错(Faulting)指令字 BADI
134 0x89 TLB重填异常出错(Faulting)虚地址 TLBRBADV
/linux/arch/xtensa/
H A DKconfig.debug47 This may simplify finding faulting code in the absence of other
/linux/Documentation/devicetree/bindings/iommu/
H A Diommu.txt19 through the IOMMU and faulting when encountering accesses to unmapped
102 having to either put back-pressure on the master, or abort new faulting
/linux/arch/microblaze/kernel/
H A Dhw_exception_handler.S204 * - < ## 32 bit faulting address ## >
488 /* If we are faulting a kernel address, we have to use the
603 /* If we are faulting a kernel address, we have to use the
673 /* If we are faulting a kernel address, we have to use the
771 /* Create EPN. This is the faulting address plus a static
905 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
/linux/arch/arc/mm/
H A Dtlbex.S157 ; This macro does the page-table lookup for the faulting address.
158 ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
172 ld.as r3, [r1, r0] ; PGD entry corresp to faulting addr
/linux/arch/sparc/mm/
H A Dfault_64.c169 /* If we were able to probe the faulting instruction, use it in do_fault_siginfo()
223 /* This was a non-faulting load. Just clear the in do_kernel_fault()
376 /* Non-faulting loads shouldn't expand stack. */ in do_sparc64_fault()
/linux/arch/hexagon/mm/
H A Dcopy_to_user.S15 * Therefore, we duplicate the function, and handle faulting addresses
/linux/arch/x86/xen/
H A DKconfig96 Use safe (not faulting) MSR access functions even if the MSR access

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