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/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,nvec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
26 - description: divider clock
27 - description: fast clock
29 clock-names:
32 - const: div-clk
33 - const: fast-clk
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7885-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 etc0: etc0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
[all …]
H A Dexynos7870-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7870 SoC pin-mux and pin-config device tree source
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include "exynos-pinctrl.h"
13 etc0: etc0-gpio-bank {
14 gpio-controller;
15 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
21 etc1: etc1-gpio-bank {
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
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/linux/drivers/hid/intel-thc-hid/intel-quicki2c/
H A Dquicki2c-dev.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/hid-over-i2c.h>
72 * struct quicki2c_subip_acpi_parameter - QuickI2C ACPI DSD parameters
88 * struct quicki2c_subip_acpi_config - QuickI2C ACPI DSD parameters
93 * @FMHX: Fast Mode (400 kbit/s) Serial Clock Line HIGH Period
94 * @FMLX: Fast Mode (400 kbit/s) Serial Clock Line LOW Period
95 * @FMTD: Fast Mode (400 kbit/s) Serial Data Line Transmit Hold Period
96 * @FMRD: Fast Mode (400 kbit/s) Serial Data Line Receive Hold Period
98 * in Standard Mode, Fast Mode and Fast Mode Plus
99 * @FPHX: Fast Mode Plus (1Mbit/sec) Serial Clock Line HIGH Period
[all …]
/linux/drivers/bus/
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
73 * FAST CSn CFG
[all …]
/linux/drivers/i2c/busses/
H A Di2c-designware-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
187 struct clk;
192 * struct dw_i2c_dev - private i2c-designware data
199 * @clk: input reference clock
225 * @rx_outstanding: current master-rx elements in tx fifo
230 * @fs_hcnt: fast speed HCNT value
231 * @fs_lcnt: fast speed LCNT value
232 * @fp_hcnt: fast plus HCNT value
233 * @fp_lcnt: fast plus LCNT value
239 * -1 if there is no semaphore.
[all …]
H A Di2c-uniphier-f.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
82 struct clk *clk; member
99 * TX-FIFO stores target address in it for the first access. in uniphier_fi2c_fill_txfifo()
103 fifo_space--; in uniphier_fi2c_fill_txfifo()
105 while (priv->len) { in uniphier_fi2c_fill_txfifo()
106 if (fifo_space-- <= 0) in uniphier_fi2c_fill_txfifo()
109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
110 priv->len--; in uniphier_fi2c_fill_txfifo()
116 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? in uniphier_fi2c_drain_rxfifo()
[all …]
H A Di2c-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
8 * based on a (non-working) driver which was:
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #include <linux/dma-mapping.h>
27 #include <linux/dma/mxs-dma.h>
29 #define DRIVER_NAME "mxs-i2c"
69 #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
71 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
[all …]
H A Di2c-meson.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
68 * struct meson_i2c - Meson I2C device private data
73 * @clk: Pointer to clock structure
90 struct clk *clk; member
116 data = readl(i2c->regs + reg); in meson_i2c_set_mask()
119 writel(data, i2c->regs + reg); in meson_i2c_set_mask()
124 i2c->tokens[0] = 0; in meson_i2c_reset_tokens()
125 i2c->tokens[1] = 0; in meson_i2c_reset_tokens()
126 i2c->num_tokens = 0; in meson_i2c_reset_tokens()
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H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
71 /* FAST MODE frequency */
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
84 /* calculate the value of CS bits in CCR register on fast mode */
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
89 /* calculate the value of CS bits in CSR register on fast mode */
95 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dimg,pistachio-gptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/img,pistachio-gptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pistachio general-purpose timer
10 - Ezequiel Garcia <ezequiel.garcia@imgtec.com>
14 const: img,pistachio-gptimer
21 - description: Timer0 interrupt
22 - description: Timer1 interrupt
23 - description: Timer2 interrupt
[all …]
/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/marvell,pxa1908.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
[all …]
/linux/drivers/spi/
H A Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
12 #include <linux/clk.h>
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
34 struct clk *clk; member
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
[all …]
H A Dspi-wpcm-fiu.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/clk.h>
10 #include <linux/spi/spi-mem.h>
53 /* The memory-mapped view of flash is 16 MiB long */
59 struct clk *clk; member
68 writeb(opcode, fiu->regs + FIU_UMA_CODE); in wpcm_fiu_set_opcode()
73 writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0); in wpcm_fiu_set_addr()
74 writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1); in wpcm_fiu_set_addr()
75 writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2); in wpcm_fiu_set_addr()
83 writeb(data[i], fiu->regs + FIU_UMA_DB0 + i); in wpcm_fiu_set_data()
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8026-lg-lenok.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include "qcom-msm8226.dtsi"
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
12 /delete-node/ &adsp_region;
17 chassis-type = "watch";
18 qcom,board-id = <132 0x0a>;
19 qcom,msm-id = <199 0x20000>;
27 stdout-path = "serial0:115200n8";
30 reserved-memory {
[all …]
H A Dqcom-msm8974-sony-xperia-rhine.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-msm8974.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 stdout-path = "serial0:115200n8";
20 gpio-keys {
21 compatible = "gpio-keys";
23 pinctrl-names = "default";
24 pinctrl-0 = <&gpio_keys_pin_a>;
[all …]
H A Dqcom-msm8974pro-fairphone-fp2.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-msm8974pro.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
12 chassis-type = "handset";
21 stdout-path = "serial0:115200n8";
24 gpio-keys {
25 compatible = "gpio-keys";
27 pinctrl-names = "default";
[all …]
/linux/drivers/clocksource/
H A Dtimer-fttmr010.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
81 * - aspeed timer overflow interrupt is controlled by bits in Control
83 * - aspeed timers always generate interrupt when either one of the
113 * fast and stateless
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
129 return ~readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_down()
[all …]
H A Dtimer-pistachio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pistachio clocksource based on general-purpose timers
10 #include <linux/clk.h>
80 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
81 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
82 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
83 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
99 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
105 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
114 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable()
[all …]
/linux/drivers/clk/at91/
H A Dclk-h32mx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-h32mx.c
7 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <linux/clk-provider.h>
12 #include <linux/clk/at91_pmc.h>
34 regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr); in clk_sama5d4_h32mx_recalc_rate()
39 pr_warn("H32MX clock is too fast\n"); in clk_sama5d4_h32mx_recalc_rate()
48 if (req->rate > req->best_parent_rate) { in clk_sama5d4_h32mx_determine_rate()
49 req->rate = req->best_parent_rate; in clk_sama5d4_h32mx_determine_rate()
53 div = req->best_parent_rate / 2; in clk_sama5d4_h32mx_determine_rate()
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
[all …]
/linux/drivers/input/misc/
H A Dadxl34x-spi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ADLX345/346 Three-Axis Digital Accelerometers (SPI Interface)
72 /* don't exceed max specified SPI CLK frequency */ in adxl34x_spi_probe()
73 if (spi->max_speed_hz > MAX_SPI_FREQ_HZ) { in adxl34x_spi_probe()
74 dev_err(&spi->dev, "SPI CLK %d Hz too fast\n", spi->max_speed_hz); in adxl34x_spi_probe()
75 return -EINVAL; in adxl34x_spi_probe()
78 ac = adxl34x_probe(&spi->dev, spi->irq, in adxl34x_spi_probe()
79 spi->max_speed_hz > MAX_FREQ_NO_FIFODELAY, in adxl34x_spi_probe()
102 MODULE_DESCRIPTION("ADXL345/346 Three-Axis Digital Accelerometer SPI Bus Driver");
/linux/drivers/rtc/
H A Drtc-ti-k3.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
8 #include <linux/clk.h>
46 #define K3RTC_MIN_OFFSET (-277761)
50 .name = "peripheral-registers",
107 * struct ti_k3_rtc - Private data for ti-k3-rtc
129 ret = regmap_field_read(priv->r_fields[f], &val); in k3rtc_field_read()
141 regmap_field_write(priv->r_fields[f], val); in k3rtc_field_write()
145 * k3rtc_fence - Ensure a register sync took place between the two domains
148 * Return: 0 if the sync took place, else returns -ETIMEDOUT
[all …]
/linux/drivers/gpu/drm/pl111/
H A Dpl111_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
7 * Copyright (c) 2006-2008 Intel Corporation
12 #include <linux/clk.h>
14 #include <linux/dma-buf.h>
15 #include <linux/media-bus-format.h>
33 irq_stat = readl(priv->regs + CLCD_PL111_MIS); in pl111_irq()
39 drm_crtc_handle_vblank(&priv->pipe.crtc); in pl111_irq()
45 writel(irq_stat, priv->regs + CLCD_PL111_ICR); in pl111_irq()
54 struct drm_device *drm = pipe->crtc.dev; in pl111_mode_valid()
[all …]

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