fast\-clk (full) in projects: linux - OpenGrok search results

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Searched +full:fast +full:- +full:clk (Results 1 – 14 of 14) sorted by relevance

/illumos-gate/usr/src/uts/i86pc/ml/
H A D	locore.S	64 * - We are running in protected-paged mode. 65 * - Interrupts are disabled. 66 * - The GDT and IDT are the callers; we need our copies. 67 * - The kernel's text, initialized data and bss are mapped. 70 * - Save arguments 71 * - Initialize our stack pointer to the thread 0 stack (t0stack) 73 * - Our GDT and IDT need to get munged. 74 * - Since we are using the boot's GDT descriptors, we need 76 * - We start using our GDT by loading correct values in the 79 * - The default LDT entry for syscall is set. [all …]
/illumos-gate/usr/src/uts/common/io/wpi/
H A D	wpi.c	`82 #include "fw-wpi/ipw3945.ucode.hex" 294 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 / 295 / R1-R4 (ral/ural is R4-R1) / 297 / CCK: device-dependent */ 422 mutex_enter(&sc->sc_glock); in wpi_attach() 423 sc->sc_flags &= ~WPI_F_SUSPEND; in wpi_attach() 424 mutex_exit(&sc->sc_glock); in wpi_attach() 426 if (sc->sc_flags & WPI_F_RUNNING) in wpi_attach() 429 mutex_enter(&sc->sc_glock); in wpi_attach() 430 sc->sc_flags \|= WPI_F_LAZY_RESUME; in wpi_attach() [all …]`
/illumos-gate/usr/src/lib/libjedec/common/
H A D	spd_ddr5.h	21 * Standard JESD400-5A.01 DDR5 Serial Presence Detect (SPD) Contents. Release 27 * o Base Configuration and DRAM parameters (0x00-0x7f) 28 * o Common Module Parameters (0xc0-0xef) 29 * o Standard Module Parameters (0xf0-0x1bf) which vary on whether something 31 * o A CRC check for the first 510 bytes (0x1fe-0x1ff) 32 * o Manufacturing Information (0x200-0x27f) 33 * o Optional end-user programmable regions (0x280-0x3ff) 407 * SPD_DDR5_SPD_REV, but covers all of the module-specific information, which 408 * includes both the common area and type-specific areas. 415 * JEDS316-5. [all …]
/illumos-gate/usr/src/uts/common/io/iwn/
H A D	if_iwn.c	1 /* $NetBSD: if_iwn.c,v 1.78 2016/06/10 13:27:14 ozaki-r Exp $ / 4 /- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 21 * Copyright 2016 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 31 * - turn tunables into driver properties 419 return (ddi_get32(sc->sc_regh, (uint32_t )(sc->sc_base + reg))); in iwn_read() 426 ddi_put32(sc->sc_regh, (uint32_t )(sc->sc_base + reg), val); in iwn_write() 432 ddi_put8(sc->sc_regh, (uint8_t )(sc->sc_base + reg), val); in iwn_write_1() 439 ks = kstat_create(ddi_driver_name(sc->sc_dip), in iwn_kstat_create() 440 ddi_get_instance(sc->sc_dip), name, "misc", KSTAT_TYPE_NAMED, in iwn_kstat_create() [all …]
/illumos-gate/usr/src/uts/common/io/yge/
H A D	yge.h	12 * are provided to you under the BSD-type license terms provided 17 * - Redistributions of source code must retain the above copyright 19 * - Redistributions in binary form must reproduce the above 23 * - Neither the name of Marvell nor the names of its contributors 57 * D-Link PCI vendor ID 91 * D-Link gigabit ethernet device ID 133 #define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) / 134 #define PCI_Y2_DLL_DIS BIT(30) / Disable PCI DLL (YUKON-2) / 135 #define PCI_Y2_PHY2_COMA BIT(29) / Set PHY 2 to Coma Mode (YUKON-2) / 136 #define PCI_Y2_PHY1_COMA BIT(28) / Set PHY 1 to Coma Mode (YUKON-2) */ [all …]
/illumos-gate/usr/src/uts/common/io/iwk/
H A D	iwk2.c	91 #include "fw-iw/iw4965.ucode.hex" 493 mutex_enter(&sc->sc_glock); in iwk_attach() 494 sc->sc_flags &= ~IWK_F_SUSPEND; in iwk_attach() 495 mutex_exit(&sc->sc_glock); in iwk_attach() 497 if (sc->sc_flags & IWK_F_RUNNING) in iwk_attach() 500 mutex_enter(&sc->sc_glock); in iwk_attach() 501 sc->sc_flags \|= IWK_F_LAZY_RESUME; in iwk_attach() 502 mutex_exit(&sc->sc_glock); in iwk_attach() 519 sc->sc_dip = dip; in iwk_attach() 521 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, in iwk_attach() [all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A D	hxge_peu_hw.h	230 * Master Data Parity Error - set if all the following conditions 234 * Fast Back-to-Back Capable (N/A in PCIE) 236 * Capabilities List - presence of extended capability item. 239 * Fast Back-to-Back Enable (N/A in PCIE) 244 * The device can issue Memory Write-and-Invalidate commands (N/A 346 * Multi-Function Device: dbi writeable 374 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0 432 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX 489 * Description: Virtualization BAR0 - Previously for Hydra 566 * Subsystem ID as assigned by PCI-SIG : dbi writeable [all …]
/illumos-gate/usr/src/uts/i86pc/io/apix/
H A D	apix.c	189 * apix_lock is used for cpu selection and vector re-binding 214 /* number of CPUs in power-on transition state */ 294 apixs[i]->x_cpuid = i; in apix_softinit() 295 LOCK_INIT_CLEAR(&apixs[i]->x_lock); in apix_softinit() 324 int cpuid = CPU->cpu_id; in apix_get_pending_spl() 326 return (bsrw_insn(apixs[cpuid]->x_intr_pending)); in apix_get_pending_spl() 338 apix_vector = apixs[cpu]->x_vectbl[vec]; in apix_get_intr_handler() 340 return ((uintptr_t)(apix_vector->v_autovect)); in apix_get_intr_handler() 360 apic_pir_vect = apix_get_ipivect(XC_CPUPOKE_PIL, -1); in apix_init() 382 highest_irq - lowest_irq + 1; in apix_init() [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 132 …G_FAST_B2B_CAP (0x1<<23) // Fast Back to Back Transa… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D	57712_reg.h	3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32 9 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 14 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 15 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 16 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 17 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… [all …]