Searched +full:eye +full:- +full:vrt (Results  1 – 4 of 4) sorted by relevance
| /linux/Documentation/devicetree/bindings/phy/ | 
| H A D | mediatek,xsphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---
 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
 8 title: MediaTek XS-PHY Controller
 11   - Chunfeng Yun <chunfeng.yun@mediatek.com>
 14   The XS-PHY controller supports physical layer functionality for USB3.1
 18   ----------------------------------
 45     pattern: "^xs-phy@[0-9a-f]+$"
 49       - enum:
 50           - mediatek,mt3611-xsphy
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| H A D | mediatek,tphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---
 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
 8 title: MediaTek T-PHY Controller
 11   - Chunfeng Yun <chunfeng.yun@mediatek.com>
 14   The T-PHY controller supports physical layer functionality for a number of
 17   Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
 18   T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
 19   -----------------------------------
 67     pattern: "^t-phy(@[0-9a-f]+)?$"
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| /linux/drivers/phy/mediatek/ | 
| H A D | phy-mtk-xsphy.c | 1 // SPDX-License-Identifier: GPL-2.010 #include <dt-bindings/phy/phy.h>
 21 #include "phy-mtk-io.h"
 106 	/* u2 eye diagram */
 124 	void __iomem *pbase = inst->port_base;  in u2_phy_slew_rate_calibrate()
 130 	if (inst->eye_src)  in u2_phy_slew_rate_calibrate()
 161 		tmp = xsphy->src_ref_clk * xsphy->src_coef;  in u2_phy_slew_rate_calibrate()
 168 	dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",  in u2_phy_slew_rate_calibrate()
 169 		inst->index, fm_out, calib_val,  in u2_phy_slew_rate_calibrate()
 170 		xsphy->src_ref_clk, xsphy->src_coef);  in u2_phy_slew_rate_calibrate()
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| H A D | phy-mtk-tphy.c | 1 // SPDX-License-Identifier: GPL-2.08 #include <dt-bindings/phy/phy.h>
 15 #include <linux/nvmem-consumer.h>
 22 #include "phy-mtk-io.h"
 24 /* version V1 sub-banks offset base address */
 35 /* version V2/V3 sub-banks offset base address */
 218 /* CDR Charge Pump P-path current adjustment */
 237 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
 246 /* I-path capacitance adjustment for Gen1 */
 279  * mtk_phy_pdata - SoC specific platform data
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