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/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
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H A Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy(@[0-9a-f]+)?$"
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
21 #include "phy-mtk-io.h"
106 /* u2 eye diagram */
124 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
130 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
161 tmp = xsphy->src_ref_clk * xsphy->src_coef; in u2_phy_slew_rate_calibrate()
168 dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", in u2_phy_slew_rate_calibrate()
169 inst->index, fm_out, calib_val, in u2_phy_slew_rate_calibrate()
170 xsphy->src_ref_clk, xsphy->src_coef); in u2_phy_slew_rate_calibrate()
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H A Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
218 /* CDR Charge Pump P-path current adjustment */
237 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
246 /* I-path capacitance adjustment for Gen1 */
279 * mtk_phy_pdata - SoC specific platform data
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/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-d4xx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-d4xx:
15 Intel D4xx (D435, D455 and others) cameras include per-frame metadata in their UVC
37 .. flat-table:: D4xx metadata
39 :header-rows: 1
40 :stub-columns: 0
42 * - **Field**
43 - **Description**
44 * - :cspan:`1` *Depth Control*
45 * - __u32 ID
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/linux/fs/nfs/
H A Dwrite.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/backing-dev.h>
83 INIT_LIST_HEAD(&p->pages); in nfs_commitdata_alloc()
105 p->rw_mode = FMODE_WRITE; in nfs_writehdr_alloc()
122 ioc->complete = complete; in nfs_io_completion_init()
123 ioc->data = data; in nfs_io_completion_init()
124 kref_init(&ioc->refcount); in nfs_io_completion_init()
131 ioc->complete(ioc->data); in nfs_io_completion_release()
138 kref_get(&ioc->refcount); in nfs_io_completion_get()
144 kref_put(&ioc->refcount, nfs_io_completion_release); in nfs_io_completion_put()
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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