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Searched +full:exynos7 +full:- +full:clk (Results 1 – 14 of 14) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos7-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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/linux/Documentation/devicetree/bindings/sound/
H A Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - $ref: dai-common.yaml#
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
25 samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7 SoC device tree source
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "samsung,exynos7";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
30 arm-pmu {
31 compatible = "arm,cortex-a57-pmu";
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H A Dexynos7-espresso.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7 Espresso board device tree source
9 /dts-v1/;
10 #include "exynos7.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/samsung,s2mps11.h>
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Samsung Exynos7 Espresso board based on Exynos7";
17 compatible = "samsung,exynos7-espresso", "samsung,exynos7";
26 stdout-path = &serial_2;
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H A Dexynos850.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/exynos850.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/samsung,exynos-usi.h>
20 #address-cells = <2>;
21 #size-cells = <1>;
23 interrupt-parent = <&gic>;
34 arm-pmu {
35 compatible = "arm,cortex-a55-pmu";
44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
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H A Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
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H A Dexynosautov9.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov9.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,boot-mode.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a76-pmu";
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H A Dexynosautov920.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h>
15 #address-cells = <2>;
16 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a78-pmu";
37 compatible = "fixed-clock";
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/linux/drivers/clk/samsung/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
7 obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o
8 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o
9 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4412-isp.o
10 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5250.o
11 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5-subcmu.o
12 obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o
13 obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o
14 obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5420.o
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/linux/drivers/i2c/busses/
H A Di2c-exynos5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
18 #include <linux/clk.h>
141 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
184 struct clk *clk; /* operating clock */ member
185 struct clk *pclk; /* bus clock */
206 /* Version of HS-I2C Hardware */
211 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
251 .compatible = "samsung,exynos5-hsi2c",
254 .compatible = "samsung,exynos5250-hsi2c",
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/linux/drivers/usb/dwc3/
H A Ddwc3-exynos.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-exynos.c - Samsung Exynos DWC3 Specific Glue layer
15 #include <linux/clk.h>
32 struct clk *clks[DWC3_EXYNOS_MAX_CLOCKS];
43 struct device *dev = &pdev->dev; in dwc3_exynos_probe()
44 struct device_node *node = dev->of_node; in dwc3_exynos_probe()
50 return -ENOMEM; in dwc3_exynos_probe()
53 exynos->dev = dev; in dwc3_exynos_probe()
54 exynos->num_clks = driver_data->num_clks; in dwc3_exynos_probe()
55 exynos->clk_names = (const char **)driver_data->clk_names; in dwc3_exynos_probe()
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/linux/drivers/watchdog/
H A Ds3c2410_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/clk.h>
92 * DOC: Quirk flags for different Samsung watchdog IP-cores
97 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk
104 * write-only, writing any values to this register clears the interrupt, but
129 * %QUIRK_HAS_32BIT_CNT: WTDAT and WTCNT are 32-bit registers. With these
130 * 32-bit registers, larger values will be set, which means that larger timeouts
166 * struct s3c2410_wdt_variant - Per-variant config data
197 struct clk *bus_clk; /* for register interface (PCLK) */
198 struct clk *src_clk; /* for WDT counter */
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/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk.h>
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
253 /* Exynos9 - GS101 */
387 for (; (tune)->region != PTR_INVALID; ++(tune))
441 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
449 * @hs_phy: pointer to non-Samsung IP high-speed phy controller
457 * @orientation: TypeC connector orientation - normal or flipped
487 phys[(inst)->index]); in to_usbdrd_phy()
524 return -EINVAL; in exynos5_rate_to_clk()
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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <linux/clk.h>
29 #include <linux/soc/samsung/exynos-pmu.h>
30 #include <linux/soc/samsung/exynos-regs-pmu.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
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