Searched +full:exynos5433 +full:- +full:pcie +full:- +full:phy (Results 1 – 5 of 5) sorted by relevance
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | samsung,exynos-pcie-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series PCIe PHY
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Jaehoon Chung <jh80.chung@samsung.com>
14 "#phy-cells":
18 const: samsung,exynos5433-pcie-phy
23 samsung,pmu-syscon:
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| /linux/drivers/phy/samsung/ |
| H A D | phy-exynos-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos SoC series PCIe PHY driver
5 * Phy provider for PCIe controller on Exynos SoC series
7 * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
15 #include <linux/phy/phy.h>
20 /* Sysreg FSYS register offsets and bits for Exynos5433 */
34 /* PMU PCIE PHY isolation control */
37 /* For Exynos pcie phy */
49 /* Exynos5433 specific functions */
50 static int exynos5433_pcie_phy_init(struct phy *phy) in exynos5433_pcie_phy_init() argument
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| /linux/arch/arm64/boot/dts/exynos/ |
| H A D | exynos5433.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC device tree source
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
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| /linux/drivers/usb/dwc3/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
19 bool "Register ULPI PHY Interface"
22 Select this if you have ULPI type PHY attached to your DWC3
74 Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
78 tristate "PCIe-based Platforms"
82 If you're using the DesignWare Core IP with a PCIe (but not HAPS
86 tristate "Synopsys PCIe-based HAPS Platforms"
90 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
189 or dual-role mode.
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| /linux/drivers/clk/samsung/ |
| H A D | clk-exynos5433.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Exynos5433 SoC.
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/exynos5433.h>
20 #include "clk-cpu.h"
21 #include "clk-exynos-arm64.h"
22 #include "clk-pll.h"
792 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
794 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
795 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
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