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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dexynos5422-dmc.txt1 * Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
3 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
9 switch the DMC and memory frequency.
11 Required properties for DMC device for Exynos5422:
12 - compatible: Should be "samsung,exynos5422-dmc".
13 - clocks : list of clock specifiers, must contain an entry for each
14 required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
17 - clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
20 - devfreq-events : phandles for PPMU devices connected to this DMC.
21 - vdd-supply : phandle for voltage regulator which is connected.
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H A Dsamsung,exynos5422-dmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Lukasz Luba <lukasz.luba@arm.com>
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
22 switch the DMC and memory frequency.
27 - const: samsung,exynos5422-dmc
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/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
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/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Dexynos-bus.txt4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
26 VDD_xxx |--- A block (parent)
27 |--- B block (passive)
28 |--- C block (passive)
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
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