Searched +full:exynos4412 +full:- +full:isp +full:- +full:clock (Results 1 – 7 of 7) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/samsung,exynos4412-isp-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Samsung Exynos4412 SoC ISP clock controller10 - Chanwoo Choi <cw00.choi@samsung.com>11 - Krzysztof Kozlowski <krzk@kernel.org>12 - Sylwester Nawrocki <s.nawrocki@samsung.com>13 - Tomasz Figa <tomasz.figa@gmail.com>16 Clock controller for Samsung Exynos4412 SoC FIMC-ISP (Camera ISP)[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Samsung Exynos SoC clock controller10 - Chanwoo Choi <cw00.choi@samsung.com>11 - Krzysztof Kozlowski <krzk@kernel.org>12 - Sylwester Nawrocki <s.nawrocki@samsung.com>13 - Tomasz Figa <tomasz.figa@gmail.com>17 dt-bindings/clock/ headers.[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Samsung's Exynos4412 SoC device tree source19 #include "exynos4-cpu-thermal.dtsi"27 fimc-lite0 = &fimc_lite_0;28 fimc-lite1 = &fimc_lite_1;31 bus_acp: bus-acp {32 compatible = "samsung,exynos-bus";33 clocks = <&clock CLK_DIV_ACP>;34 clock-names = "bus";35 operating-points-v2 = <&bus_acp_opp_table>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Samsung's Exynos4412 based Galaxy S3 board device tree source9 /dts-v1/;10 #include <dt-bindings/leds/common.h>11 #include "exynos4412-midas.dtsi"19 led-controller {21 flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>;22 enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>;24 pinctrl-names = "default", "host", "isp";25 pinctrl-0 = <&camera_flash_host>;[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */6 * Device Tree binding constants for Exynos4 clock controller.54 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */82 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */123 #define CLK_MDNIE0 285 /* Exynos4412 only */214 /* gate clocks - ppmu */242 /* Exynos4x12 ISP clocks */
1 # SPDX-License-Identifier: GPL-2.03 # Samsung Clock specific Makefile6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o7 obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o8 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o9 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4412-isp.o10 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5250.o11 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5-subcmu.o12 obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o13 obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later5 * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd.24 #include <media/v4l2-ioctl.h>25 #include <media/videobuf2-v4l2.h>26 #include <media/videobuf2-dma-contig.h>28 #include "fimc-core.h"29 #include "fimc-reg.h"30 #include "media-dev.h"197 if (!ctx->scaler.enabled) in fimc_check_scaler_ratio()198 return (sw == dw && sh == dh) ? 0 : -EINVAL; in fimc_check_scaler_ratio()[all …]