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Searched +full:exynos4412 +full:- +full:isp +full:- +full:clock (Results 1 – 8 of 8) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dexynos4-clock.txt1 * Samsung Exynos4 Clock Controller
3 The Exynos4 clock controller generates and supplies clock to various controllers
4 within the Exynos4 SoC. The clock binding described here is applicable to all
9 - compatible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume.
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H A Dsamsung,exynos4412-isp-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos4412-isp-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos4412 SoC ISP clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Clock controller for Samsung Exynos4412 SoC FIMC-ISP (Camera ISP)
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H A Dsamsung,exynos-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 dt-bindings/clock/ headers.
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dexynos4-fimc-is.txt1 Exynos4x12 SoC series Imaging Subsystem (FIMC-IS)
3 The FIMC-IS is a subsystem for processing image signal from an image sensor.
4 The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
5 processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C
8 fimc-is node
9 ------------
12 - compatible : should be "samsung,exynos4212-fimc-is" for Exynos4212 and
13 Exynos4412 SoCs;
14 - reg : physical base address and length of the registers set;
15 - interrupts : must contain two FIMC-IS interrupts, in order: ISP0, ISP1;
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 SoC device tree source
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bu
281 clock: clock-controller@10030000 { global() label
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H A Dexynos4412-galaxy-s3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 based Galaxy S3 board device tree source
9 /dts-v1/;
10 #include <dt-bindings/leds/common.h>
11 #include "exynos4412-midas.dtsi"
19 led-controller {
21 flen-gpio
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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dexynos4.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Device Tree binding constants for Exynos4 clock controller.
54 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
82 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
123 #define CLK_MDNIE0 285 /* Exynos4412 only */
214 /* gate clocks - ppmu */
242 /* Exynos4x12 ISP clocks */
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Dexynos-bus.txt4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
5 for buses. Generally, each bus of Exynos SoC includes a source clock
6 and a power line, which are able to change the clock frequency
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
12 The each AXI bus has the owned source clock but, has not the only owned
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
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