/linux/drivers/net/phy/ |
H A D | nxp-c45-tja11xx.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright 2021-2023 NXP 4 * Author: Radu Pirea <radu-nicolae.pirea@oss.nxp.com> 20 #include "nxp-c45-tja11xx.h" 195 #define NXP_C45_SKB_CB(skb) ((struct nxp_c45_skb_cb *)(skb)->cb) 290 bool (*get_extts)(struct nxp_c45_phy *priv, struct timespec64 *extts); 300 return phydev->drv->driver_data; in nxp_c45_get_data() 308 return phy_data->regmap; in nxp_c45_get_regmap() 317 if (reg_field->size == 0) { in nxp_c45_read_reg_field() 319 return -EINVAL; in nxp_c45_read_reg_field() [all …]
|
H A D | micrel.c | 1 // SPDX-License-Identifier: GPL-2.0+ 9 * Copyright (c) 2010-2013 Micrel, Inc. 126 * The value is calculated as following: (1/1000000)/((2^-32)/4) 132 * The value is calculated as following: (1/1000000)/((2^-32)/8) 413 /* Lock for Rx ts fifo */ 527 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr() 531 if (type && type->interrupt_level_mask) in kszphy_config_intr() 532 mask = type->interrupt_level_mask; in kszphy_config_intr() 544 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in kszphy_config_intr() 607 return -EINVAL; in kszphy_setup_led() [all …]
|
/linux/Documentation/devicetree/bindings/ptp/ |
H A D | fsl,ptp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <Frank.Li@nxp.com> 15 - enum: 16 - fsl,etsec-ptp 17 - fsl,fman-ptp-timer 18 - fsl,dpaa2-ptp 19 - items: 20 - const: pci1957,ee02 [all …]
|
/linux/arch/arm64/boot/dts/freescale/ |
H A D | qoriq-fman3-0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 5 * Copyright 2012-2015 Freescale Semiconductor Inc. 9 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #address-cells = <1>; 13 #size-cells = <1>; 14 cell-index = <0>; 21 clock-names = "fmanclk"; 22 fsl,qman-channel-range = <0x800 0x10>; 23 ptimer-handle = <&ptp_timer0>; 24 dma-coherent; [all …]
|
H A D | fsl-ls1088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1088A family SoC. 5 * Copyright 2017-2020 NXP 10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 26 #address-cells = <1>; [all …]
|
H A D | fsl-ls208xa.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 6 * Copyright 2017-2020 NXP 12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/interrupt-controller/arm-gic.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 32 #address-cells = <1>; [all …]
|
H A D | fsl-ls1028a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 5 * Copyright 2018-2020 NXP 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 22 #address-cells = <1>; [all …]
|
H A D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 // Device Tree Include file for Layerscape-LX2160A family SoC. 5 // Copyright 2018-2020 NXP 7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; [all …]
|
/linux/drivers/net/dsa/sja1105/ |
H A D | sja1105_ptp.c | 1 // SPDX-License-Identifier: GPL-2.0 7 /* The adjfine API clamps ppb between [-32,768,000, 32,768,000], and 8 * therefore scaled_ppm between [-2,147,483,648, 2,147,483,647]. 11 * Percentually speaking, this is a +/- 0.032x adjustment of the 12 * free-running counter (0.968x to 1.032x). 20 * one-shot toggle (no return to level) on the PTP_CLK pin. When used as a 21 * generic extts source, the PTPSYNCTS register needs polling and a comparison 25 * frequency than 1 Hz will be lost, since there is no timestamp FIFO. 29 /* This range is actually +/- SJA1105_MAX_ADJ_PPB 30 * divided by 1000 (ppb -> ppm) and with a 16-bit [all …]
|
/linux/drivers/ptp/ |
H A D | ptp_sysfs.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * PTP 1588 clock support - sysfs interface. 17 return sysfs_emit(page, "%s\n", ptp->info->name); in clock_name_show() 27 return sysfs_emit(page, "%d\n", ptp->info->getmaxphase(ptp->info)); in max_phase_adjustment_show() 36 return sysfs_emit(page, "%d\n", ptp->info->var); \ 52 struct ptp_clock_info *ops = ptp->info; in extts_enable_store() 55 int err = -EINVAL; in extts_enable_store() 57 cnt = sscanf(buf, "%u %d", &req.extts.index, &enable); in extts_enable_store() 60 if (req.extts.index >= ops->n_ext_ts) in extts_enable_store() 63 err = ops->enable(ops, &req, enable ? 1 : 0); in extts_enable_store() [all …]
|
H A D | ptp_qoriq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 26 /* Caller must hold ptp_qoriq->lock. */ 29 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_read() 33 lo = ptp_qoriq->read(®s->ctrl_regs->tmr_cnt_l); in tmr_cnt_read() 34 hi = ptp_qoriq->read(®s->ctrl_regs->tmr_cnt_h); in tmr_cnt_read() 40 /* Caller must hold ptp_qoriq->lock. */ 43 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_write() 47 ptp_qoriq->write(®s->ctrl_regs->tmr_cnt_l, lo); in tmr_cnt_write() 48 ptp_qoriq->write(®s->ctrl_regs->tmr_cnt_h, hi); in tmr_cnt_write() 53 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_offset_read() [all …]
|
H A D | ptp_fc3.c | 1 // SPDX-License-Identifier: GPL-2.0+ 27 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>"); 33 * over-rides any automatic selection 44 sync = div_u64_rem(nsec, idtfc3->ns_per_sync, &rem); in ns2counters() 47 sync = -div_u64_rem(-nsec - 1, idtfc3->ns_per_sync, &rem) - 1; in ns2counters() 48 *sub_ns = idtfc3->ns_per_sync - rem - 1; in ns2counters() 51 return sync * idtfc3->ns_per_sync; in ns2counters() 59 coarse = sign_extend64(FIELD_GET(COARSE_MEAS_MASK, meas_read), (39 - 13)); in tdc_meas2offset() 61 fine = div64_s64(fine * NSEC_PER_SEC, idtfc3->tdc_apll_freq * 62LL); in tdc_meas2offset() 62 coarse = div64_s64(coarse * NSEC_PER_SEC, idtfc3->time_ref_freq); in tdc_meas2offset() [all …]
|
/linux/drivers/net/ethernet/intel/ice/ |
H A D | ice_ptp.c | 1 // SPDX-License-Identifier: GPL-2.0 20 { TIME_SYNC, { 4, -1 }, { 0, 0 }}, 21 { ONE_PPS, { -1, 5 }, { 0, 11 }}, 30 { TIME_SYNC, { 4, -1 }, { 11, 0 }}, 31 { ONE_PPS, { -1, 5 }, { 0, 9 }}, 40 { ONE_PPS, { -1, 5 }, { 0, 1 }}, 53 { GNSS, { 1, -1 }, { 0, 0 }}, 55 { UFL1, { -1, 0 }, { 0, 1 }}, 57 { UFL2, { 3, -1 }, { 0, 0 }}, 62 return !pf->adapter ? NULL : pf->adapter->ctrl_pf; in ice_get_ctrl_pf() [all …]
|
/linux/drivers/net/ethernet/microchip/lan966x/ |
H A D | lan966x_ptp.c | 1 // SPDX-License-Identifier: GPL-2.0+ 12 * The value is calculated as following: (1/1000000)/((2^-59)/6.037735849) 57 struct lan966x *lan966x = port->lan966x; in lan966x_ptp_add_trap() 61 vrule = vcap_get_rule(lan966x->vcap_ctrl, rule_id); in lan966x_ptp_add_trap() 68 mask &= ~BIT(port->chip_port); in lan966x_ptp_add_trap() 76 vrule = vcap_alloc_rule(lan966x->vcap_ctrl, port->dev, in lan966x_ptp_add_trap() 103 struct lan966x *lan966x = port->lan966x; in lan966x_ptp_del_trap() 108 vrule = vcap_get_rule(lan966x->vcap_ctrl, rule_id); in lan966x_ptp_del_trap() 110 return -EEXIST; in lan966x_ptp_del_trap() 113 mask |= BIT(port->chip_port); in lan966x_ptp_del_trap() [all …]
|
/linux/drivers/net/ethernet/ti/ |
H A D | am65-cpts.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 9 #include <linux/clk-provider.h> 23 #include "am65-cpts.h" 201 #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r) 202 #define am65_cpts_read32(c, r) readl(&(c)->reg->r) 219 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; in am65_cpts_set_add_val() 221 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val); in am65_cpts_set_add_val() 232 return (event->event1 & AM65_CPTS_EVENT_1_PORT_NUMBER_MASK) >> in am65_cpts_event_get_port() 238 return (event->event1 & AM65_CPTS_EVENT_1_EVENT_TYPE_MASK) >> in am65_cpts_event_get_type() [all …]
|
/linux/arch/arm/boot/dts/nxp/ls/ |
H A D | ls1021a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/thermal/thermal.h> 10 #address-cells = <2>; 11 #size-cells = <2>; 12 interrupt-parent = <&gic>; 30 #address-cells = <1>; 31 #size-cells = <0>; 34 compatible = "arm,cortex-a7"; [all …]
|