| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | samsung,exynosautov9-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanho Park <chanho61.park@samsung.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
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| H A D | samsung,exynos850-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sam Protsenko <semen.protsenko@linaro.org>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
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| H A D | google,gs101-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Griffin <peter.griffin@linaro.org>
16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 'dt-bindings/clock/gs101.h' header.
30 - google,gs101-cmu-top
31 - google,gs101-cmu-apm
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| H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
16 connected with an external fixed rate oscillator, which signal is transformed
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
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| H A D | samsung,exynos7885-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dávid Virág <virag.david003@gmail.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
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| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-cc
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| /freebsd/lib/libpmc/pmu-events/arch/x86/bonnell/ |
| H A D | other.json | 3 "BriefDescription": "Bus queue is empty.",
11 "BriefDescription": "Number of Bus Not Ready signals asserted.",
19 "BriefDescription": "Number of Bus Not Ready signals asserted.",
27 "BriefDescription": "Bus cycles while processor receives data.",
35 "BriefDescription": "Bus cycles when data is sent on the bus.",
43 "BriefDescription": "Bus cycles when data is sent on the bus.",
83 "BriefDescription": "IO requests waiting in the bus queue.",
91 "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
99 "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
107 "BriefDescription": "Outstanding cacheable data read bus requests duration.",
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | pci.txt | 1 PCI bus bridges have standardized Device Tree bindings:
3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
27 - reset-gpios:
30 - supports-clkreq:
34 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
36 PCI-PCI Bridge properties
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | renesas,bsc.yaml | 2 ---
3 $id: http://devicetree.org/schemas/bus/renesas,bsc.yaml#
4 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 title: Renesas Bus State Controller (BSC)
9 - Geert Uytterhoeven <geert+renesas@glider.be>
12 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
13 Bridge", or "External Bus Interface") can be found in several Renesas ARM
14 SoCs. It provides an external bus for connecting multiple external
18 While the BSC is a fairly simple memory-mapped bus, it may be part of a
24 The bindings for the BSC extend the bindings for "simple-pm-bus".
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| H A D | qcom,ebi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm External Bus Interface 2 (EBI2)
11 external memory (such as NAND or other memory-mapped peripherals) whereas
14 As it says it connects devices to an external bus interface, meaning address
15 lines (up to 9 address lines so can only address 1KiB external memory space),
20 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
21 and the bus can only come out on these pins, however if some of the pins are
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| H A D | nvidia,tegra20-gmi.txt | 1 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
3 The Generic Memory Interface bus enables memory transfers between internal and
4 external memory. Can be used to attach various high speed devices such as
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
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| H A D | qcom,ebi2.txt | 1 Qualcomm External Bus Interface 2 (EBI2)
4 external memory (such as NAND or other memory-mapped peripherals) whereas
7 As it says it connects devices to an external bus interface, meaning address
8 lines (up to 9 address lines so can only address 1KiB external memory space),
13 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
14 and the bus can only come out on these pins, however if some of the pins are
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
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| /freebsd/sys/contrib/device-tree/Bindings/iio/imu/ |
| H A D | adi,adis16480.txt | 6 - compatible: Must be one of
12 * "adi,adis16495-1"
13 * "adi,adis16495-2"
14 * "adi,adis16495-3"
15 * "adi,adis16497-1"
16 * "adi,adis16497-2"
17 * "adi,adis16497-3"
18 - reg: SPI chip select number for the device
19 - spi-max-frequency: Max SPI frequency to use
20 see: Documentation/devicetree/bindings/spi/spi-bus.txt
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| /freebsd/sys/contrib/device-tree/Bindings/c6x/ |
| H A D | emifa.txt | 1 External Memory Interface
2 -------------------------
4 The emifa node describes a simple external bus controller found on some C6X
5 SoCs. This interface provides external busses with a number of chip selects.
9 - compatible: must be "ti,c64x+emifa", "simple-bus"
10 - reg: register area base and size
11 - #address-cells: must be 2 (chip-select + offset)
12 - #size-cells: must be 1
13 - ranges: mapping from EMIFA space to parent space
18 - ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | mt7530.txt | 6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
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| H A D | qca8k.txt | 5 - compatible: should be one of:
10 - #size-cells: must be 0
11 - #address-cells: must be 1
15 - reset-gpios: GPIO to be used to reset the whole device
20 described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
21 mdio-bus each subnode describing a port needs to have a valid phandle
24 To declare the internal mdio-bus configuration, declare a mdio node in the
26 PHY is connected to. In this config a internal mdio-bus is registered and
29 Don't use mixed external and internal mdio-bus configurations, as this is
36 - fixed-link : Fixed-link subnode describing a link to a non-MDIO
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| H A D | marvell.txt | 2 ----------
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| /freebsd/sys/dts/arm/ |
| H A D | annapurna-alpine.dts | 1 /*-
28 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a15";
47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
49 d-cache-size = <0x8000>; // L1, 32K
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | allwinner,sun8i-a83t-emac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Che
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| H A D | fsl,fman-mdio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
19 - fsl,fman-xmdio
20 - fsl,fman-memac-mdio
22 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
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| H A D | fsl-enetc.txt | 4 external) there are two supported link modes specified by
9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
20 external phy. Below properties are required, their bindings
26 - phy-handle : Phandle to a PHY on the MDIO bus.
29 - phy-connection-type : Defined in ethernet.txt.
31 - mdio : "mdio" node, defined in mdio.txt.
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6q-gk802.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
11 compatible = "zealz,imx6q-gk802", "fsl,imx6q";
14 stdout-path = &uart4;
22 reg_3p3v: regulator-
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | adi,ad7944.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 A family of pin-compatible single channel differential analog to digital
21 $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - adi,ad7944
27 - adi,ad7985
28 - adi,ad7986
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | chipidea,usb2-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
25 clock-names:
31 power-domains:
37 reset-names:
40 "#reset-cells":
45 itc-setting:
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| /freebsd/sys/dev/aic7xxx/ |
| H A D | aic7xxx.reg | 1 /*-
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
47 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
48 * Adaptec's Technical Documents Department 1-800-934-2766
52 * SCSI Sequence Control (p. 3-11).
53 * Each bit, when set starts a specific SCSI sequence on the bus
69 * SCSI Transfer Control 0 Register (pp. 3-13).
85 * SCSI Transfer Control 1 Register (pp. 3-14,15).
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