Home
last modified time | relevance | path

Searched +full:exit +full:- +full:latency (Results 1 – 25 of 250) sorted by relevance

12345678910

/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
22 enter/exit specific idle states on a given processor.
27 - Running
[all …]
H A Dpsci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
25 r0 => 32-bi
[all...]
H A Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
[all …]
H A Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
[all …]
/freebsd/sys/contrib/device-tree/Bindings/power/
H A Ddomain-idle-state.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: domain-idle-states
21 "^(cpu|cluster|domain)-":
29 const: domain-idle-state
31 entry-latency-us:
33 The worst case latency in microseconds required to enter the idle
[all …]
H A Dpower-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevi
[all...]
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dthermal-idle.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
27 '#cooling-cells':
31 the cooling-maps reference. The first cell is the minimum cooling state
34 duration-us:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/msm/
H A Dqcom,idle-state.txt3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
6 The idle states supported by the QCOM SoC are defined as -
31 state. Retention may have a slightly higher latency than Standby.
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
52 power modes possible at this state is vast, the exit latency and the residency
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 interrupt-parent = <&intc>;
[all …]
H A Dsdm630.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/interconnect/qcom,sdm660.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-supply = <&ppvar_sys>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&ap_edp_bklten>;
37 /* FIXED REGULATORS - parents above children */
[all …]
/freebsd/usr.bin/nfsstat/
H A Dnfsstat.138 .Op Fl -libxo
53 .Bl -tag -width "-w wait"
62 It also includes the current queue depth, the busy percentage, and latency
66 flag is added, commits per second, commit latency, read latency, and write
67 latency are also added to the display.
97 will exit after completing the report.
121 .It Fl -libxo
/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
[all …]
/freebsd/share/man/man9/
H A Dcritical_enter.930 .Nd enter and exit a critical region
50 When this occurs the interrupt exit will not result in a context switch, and
54 filtered interrupt handlers do not incur a latency penalty.
60 functions manage a per-thread counter to handle nested critical sections.
66 Note that these functions do not provide any inter-CPU synchronization, data
82 Abuse of critical sections has an effect on overall system latency and timer
/freebsd/sys/sys/
H A Dsmr.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 * algorithm, and smr_types.h for macros to define and access SMR-protected
39 * Readers synchronize with smr_enter()/exit() and writers may either
47 #define SMR_SEQ_LT(a, b) ((smr_delta_t)((a)-(b)) < 0)
48 #define SMR_SEQ_LEQ(a, b) ((smr_delta_t)((a)-(b)) <= 0)
49 #define SMR_SEQ_GT(a, b) ((smr_delta_t)((a)-(b)) > 0)
50 #define SMR_SEQ_GEQ(a, b) ((smr_delta_t)((a)-(b)) >= 0)
51 #define SMR_SEQ_DELTA(a, b) ((smr_delta_t)((a)-(b)))
72 /* Per-cpu SMR state. */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp1 //===- MCSchedule.cpp - Scheduling --------
44 int Latency = 0; computeInstrLatency() local
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3660.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-r2.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
[all …]
H A Djuno.dts4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
[all …]
H A Djuno-r1.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/powerpc/opal/
H A Dpower-mgt.txt1 IBM Power-Management Bindings
6 node @power-mgt in the device-tree by the firmware.
9 ----------------
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
15 extent of state-loss, whether timebase is stopped on this
18 - exit-latency: The latency involved in transitioning the state of the
21 - target-residency: The minimum time that the CPU needs to reside in
22 this idle state in order to accrue power-savings
26 ----------------
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_unit_adapter_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
82 #define AL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
83 #define AL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
87 #define AL_PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
93 #define AL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
106 #define AL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
117 #define AL_PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
118 #define AL_PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
277 /* Central Target-ID enabler. If set, then each entry will be used as programmed */
[all …]
/freebsd/sys/contrib/openzfs/cmd/zpool_influxdb/
H A DREADME.md6 stdout. In many ways, this is a metrics-friendly output of
18 |---|---|---|
19 | --execd | -e | For use with telegraf's `execd` plugin. When [enter] is pressed, the pools are sam…
20 | --no-histogram | -n | Do not print histogram information |
21 | --signed-int | -i | Use signed integer data type (default=unsigned) |
22 | --sum-histogram-buckets | -s | Sum histogram bucket values |
23 | --tags key=value[,key=value...] | -t | Add tags to data points. No tag sanity checking is perform…
24 | --help | -h | Print a short usage message |
28 This works well out-of-the-box with an influxdb data source and grafana's
35 Another method for storing histogram data sums the values for lower-value
[all …]
/freebsd/contrib/llvm-project/llvm/tools/llvm-xray/
H A Dxray-account.h1 //===- xray-account.h - XRay Function Call Accounting -------
63 recordLatency(int32_t FuncId,uint64_t Latency) recordLatency() argument
[all...]

12345678910