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/linux/drivers/hwtracing/coresight/
H A Dcoresight-kunit-tests.c23 * Source -> ETF -> ETR -> CATU in test_default_sink()
30 *etr = coresight_test_device(dev), in test_default_sink() local
42 etr->type = CORESIGHT_DEV_TYPE_SINK; in test_default_sink()
43 etr->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; in test_default_sink()
51 conn.dest_dev = etr; in test_default_sink()
54 conn.src_dev = etr; in test_default_sink()
56 coresight_add_out_conn(dev, etr->pdata, &conn); in test_default_sink()
58 KUNIT_ASSERT_PTR_EQ(test, coresight_find_default_sink(src), etr); in test_default_sink()
H A Dcoresight-tmc.h123 /* TMC ETR Capability bit definitions */
125 /* ETR has separate read/write cache encodings */
137 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */
141 /* TMC metadata region for ETR and ETF configurations */
146 uint32_t valid; /* Indicate if this ETF/ETR was enabled */
162 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
171 * struct etr_buf - Details of the buffer used by ETR
173 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc.
179 * @ops : ETR buffer operations for the mode.
226 * @etr_buf: details of buffer used in TMC-ETR
[all …]
H A Dcoresight-tmc-etr.c37 * etr_perf_buffer - Perf buffer used for ETR
38 * @drvdata - The ETR drvdaga this buffer has been allocated for.
39 * @etr_buf - Actual buffer used by the ETR
55 /* Convert the perf index to an offset within the ETR buffer */
59 /* Lower limit for ETR hardware buffer */
63 * The TMC ETR SG has a page size of 4K. The SG table contains pointers
108 * struct etr_sg_table : ETR SG Table
561 * tmc_init_etr_sg_table: Allocate a TMC ETR SG table, data buffer of @size and
847 * TMC ETR could be connected to a CATU device, which can provide address
849 * (ETR) connected to the input port of the CATU.
[all …]
H A Dcoresight-ctcu-core.c29 * filter function based on the trace ID for each TMC ETR sink. The length of each
30 * ATID register is 32 bits. Therefore, an ETR device has a 128-bit long field
89 * @port_num: port number connected to TMC ETR sink.
H A Dcoresight-catu.c80 * The base input address (used by the ETR, programmed in INADDR_{LO,HI})
312 * ETR started off at etr_buf->hwaddr. Convert the RRP/RWP to in catu_sync_etr_buf()
555 /* Default to the 40bits as supported by TMC-ETR */ in __catu_probe()
/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8973.yaml74 maxim,enable-etr:
78 maxim,enable-high-etr-sensitivity:
82 sensitivity. If this property is available then etr will be enable
84 Enhanced transient response (ETR) will affect the configuration of CKADV.
137 maxim,enable-etr;
/linux/Documentation/trace/coresight/
H A Dpanic.rst37 For ETR sink devices, this reserved region will be used for both trace
53 Comparator --->External out --->CTI -->External In---->ETR/ETF stop
59 ETR/ETF/ETB register snapshot etc.
62 the ETR/ETF/ETB device nodes for this.
73 ETR sinks should have trace buffers allocated from reserved memory,
109 Sample commands for testing a Kernel panic case with ETR sink
141 #ETR Flush in from Channel 0
169 echo "ETR CTI config for $i"
179 4. Choose reserved buffer mode for ETR buffer::
355 ETR::
H A Dcoresight-ect.rst27 # #<-----------: : +---# ETR #
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c543 "ETR buffer address shouldn't exceed 50 bits\n"); in gaudi_etr_validate_address()
549 "ETR buffer size %llu overflow\n", size); in gaudi_etr_validate_address()
573 dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n"); in gaudi_etr_validate_address()
603 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi_config_etr()
610 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi_config_etr()
627 "ETR buffer size should be bigger than 0\n"); in gaudi_config_etr()
634 dev_err(hdev->dev, "ETR buffer address is invalid\n"); in gaudi_config_etr()
646 /* make ETR not privileged */ in gaudi_config_etr()
649 /* make ETR non-secured (inverted logic) */ in gaudi_config_etr()
917 dev_err(hdev->dev, "halt ETR failed, %d\n", rc); in gaudi_halt_coresight()
/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c375 "ETR buffer size %llu overflow\n", size); in goya_etr_validate_address()
407 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in goya_config_etr()
414 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in goya_config_etr()
429 "ETR buffer size should be bigger than 0\n"); in goya_config_etr()
443 /* make ETR not privileged */ in goya_config_etr()
445 /* make ETR non-secured (inverted logic) */ in goya_config_etr()
712 dev_err(hdev->dev, "halt ETR failed, %d\n", rc); in goya_halt_coresight()
/linux/include/dt-bindings/memory/
H A Dtegra186-mc.h191 /* ETR reads */
193 /* ETR writes */
H A Dtegra194-mc.h211 /* ETR read clients */
213 /* ETR write clients */
H A Dtegra234-mc.h363 /* ETR read clients */
365 /* ETR write clients */
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpsoc_etr_regs.h18 * PSOC_ETR (Prototype: ETR)
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_etr_regs.h19 * (Prototype: ETR)
H A Dpsoc_etr_masks.h19 * (Prototype: ETR)
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dpsoc_etr_regs.h18 * PSOC_ETR (Prototype: ETR)
/linux/arch/arm64/boot/dts/arm/
H A Djuno-scmi.dtsi14 etr@20070000 {
/linux/drivers/regulator/
H A Dmax8973-regulator.c551 etr_enable = of_property_read_bool(np, "maxim,enable-etr"); in max8973_parse_dt()
553 "maxim,enable-high-etr-sensitivity"); in max8973_parse_dt()
/linux/drivers/bus/
H A Dstm32_rifsc.c98 "ETR",
117 "ETR",
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660-coresight.dtsi432 etr@ec033000 {
H A Dhi6220-coresight.dtsi99 etr@f6404000 {
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8998-mtp.dts111 &etr {
H A Dapq8016-schneider-hmibsc.dts519 &etr { status = "okay"; };
/linux/drivers/memory/tegra/
H A Dtegra210.c1201 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1272 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),

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