| /linux/drivers/hwtracing/coresight/ |
| H A D | coresight-tmc.h | 116 /* TMC ETR Capability bit definitions */
118 /* ETR has separate read/write cache encodings */
130 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */
136 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
144 * struct etr_buf - Details of the buffer used by ETR
146 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc.
152 * @ops : ETR buffer operations for the mode.
178 * @etr_buf: details of buffer used in TMC-ETR
182 * TMC-ETR on AXI bus.
186 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the
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| H A D | coresight-tmc-etr.c | 36 * etr_perf_buffer - Perf buffer used for ETR
37 * @drvdata - The ETR drvdaga this buffer has been allocated for.
38 * @etr_buf - Actual buffer used by the ETR
54 /* Convert the perf index to an offset within the ETR buffer */
58 /* Lower limit for ETR hardware buffer */
62 * The TMC ETR SG has a page size of 4K. The SG table contains pointers
107 * struct etr_sg_table : ETR SG Table
560 * tmc_init_etr_sg_table: Allocate a TMC ETR SG table, data buffer of @size and
777 * TMC ETR could be connected to a CATU device, which can provide address
779 * (ETR) connected to the input port of the CATU.
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| H A D | Kconfig | 41 trace router - ETR) or sink (embedded trace FIFO). The driver
54 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
55 buffer by translating the addresses used by ETR to the physical address
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| H A D | coresight-tmc-core.c | 378 * as ETR. in tmc_etr_can_use_sg()
401 /* Detect and initialise the capabilities of a TMC ETR */
428 * Unless specified in the device configuration, ETR uses a 40-bit in tmc_etr_setup_caps()
636 /* Coresight SoC 600 TMC-ETR/ETS */
724 {"ARMHC501", 0, 0, 0}, /* ARM CoreSight ETR */
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| H A D | Makefile | 32 coresight-tmc-etr.o
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| H A D | coresight-catu.c | 80 * The base input address (used by the ETR, programmed in INADDR_{LO,HI})
313 * ETR started off at etr_buf->hwaddr. Convert the RRP/RWP to in catu_sync_etr_buf()
538 /* Default to the 40bits as supported by TMC-ETR */ in __catu_probe()
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,coresight-tmc.yaml | 24 FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
25 mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
68 Size of contiguous buffer space for TMC ETR (embedded trace router). The
75 Indicates that the TMC-ETR can safely use the SG mode on this system.
100 description: AXI or ATB Master output connection. Used for ETR
115 etr@20070000 {
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| H A D | arm,embedded-trace-extension.yaml | 19 components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
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| /linux/Documentation/devicetree/bindings/regulator/ |
| H A D | maxim,max8973.yaml | 74 maxim,enable-etr:
78 maxim,enable-high-etr-sensitivity:
82 sensitivity. If this property is available then etr will be enable
84 Enhanced transient response (ETR) will affect the configuration of CKADV.
137 maxim,enable-etr;
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| /linux/drivers/accel/habanalabs/gaudi/ |
| H A D | gaudi_coresight.c | 543 "ETR buffer address shouldn't exceed 50 bits\n"); in gaudi_etr_validate_address()
549 "ETR buffer size %llu overflow\n", size); in gaudi_etr_validate_address()
573 dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n"); in gaudi_etr_validate_address()
603 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi_config_etr()
610 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi_config_etr()
627 "ETR buffer size should be bigger than 0\n"); in gaudi_config_etr()
634 dev_err(hdev->dev, "ETR buffer address is invalid\n"); in gaudi_config_etr()
646 /* make ETR not privileged */ in gaudi_config_etr()
649 /* make ETR non-secured (inverted logic) */ in gaudi_config_etr()
917 dev_err(hdev->dev, "halt ETR failed, %d\n", rc); in gaudi_halt_coresight()
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| /linux/drivers/accel/habanalabs/goya/ |
| H A D | goya_coresight.c | 375 "ETR buffer size %llu overflow\n", size); in goya_etr_validate_address()
407 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in goya_config_etr()
414 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in goya_config_etr()
429 "ETR buffer size should be bigger than 0\n"); in goya_config_etr()
443 /* make ETR not privileged */ in goya_config_etr()
445 /* make ETR non-secured (inverted logic) */ in goya_config_etr()
712 dev_err(hdev->dev, "halt ETR failed, %d\n", rc); in goya_halt_coresight()
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| /linux/drivers/crypto/intel/qat/qat_common/ |
| H A D | adf_common_drv.h | 253 struct adf_bar *etr; in adf_get_etr_base() local
255 etr = &GET_BARS(accel_dev)[hw_data->get_etr_bar_id(hw_data)]; in adf_get_etr_base()
257 return etr->virt_addr; in adf_get_etr_base()
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| /linux/include/dt-bindings/memory/ |
| H A D | tegra186-mc.h | 191 /* ETR reads */
193 /* ETR writes */
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| H A D | tegra194-mc.h | 211 /* ETR read clients */
213 /* ETR write clients */
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| H A D | tegra234-mc.h | 363 /* ETR read clients */
365 /* ETR write clients */
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| /linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
| H A D | psoc_etr_regs.h | 18 * PSOC_ETR (Prototype: ETR)
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| /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
| H A D | psoc_etr_regs.h | 19 * (Prototype: ETR)
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| H A D | psoc_etr_masks.h | 19 * (Prototype: ETR)
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| /linux/drivers/accel/habanalabs/include/gaudi/asic_reg/ |
| H A D | psoc_etr_regs.h | 18 * PSOC_ETR (Prototype: ETR)
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| /linux/Documentation/trace/coresight/ |
| H A D | coresight.rst | 111 TMC-ETR:
123 Funnel, replicator (intelligent or not), TMC-ETR
212 20070000.etr 20120000.replicator 220c0000.funnel
303 <file details> out:1 -> ../../../20070000.etr/tmc_etr0
326 <file details> tmc_etr0 -> ../../../20070000.etr/tmc_etr0
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| H A D | coresight-ect.rst | 27 # #<-----------: : +---# ETR #
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| /linux/drivers/accel/habanalabs/gaudi2/ |
| H A D | gaudi2_coresight.c | 2155 dev_err(hdev->dev, "ETR buffer size %llu overflow\n", size); in gaudi2_etr_validate_address()
2187 dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n"); in gaudi2_etr_validate_address()
2217 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi2_config_etr()
2224 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi2_config_etr()
2238 dev_err(hdev->dev, "ETR buffer size should be bigger than 0\n"); in gaudi2_config_etr()
2243 dev_err(hdev->dev, "ETR buffer address is invalid\n"); in gaudi2_config_etr()
2258 /* make ETR not privileged */ in gaudi2_config_etr()
2260 /* make ETR non-secured (inverted logic) */ in gaudi2_config_etr()
2596 dev_err(hdev->dev, "halt ETR failed, %d\n", rc); in gaudi2_halt_coresight()
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| /linux/arch/arm64/boot/dts/arm/ |
| H A D | juno-scmi.dtsi | 14 etr@20070000 {
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| /linux/drivers/regulator/ |
| H A D | max8973-regulator.c | 551 etr_enable = of_property_read_bool(np, "maxim,enable-etr"); in max8973_parse_dt()
553 "maxim,enable-high-etr-sensitivity"); in max8973_parse_dt()
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| /linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hi3660-coresight.dtsi | 424 etr@ec033000 {
|