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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1046-post.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2015-2016 Freescale Semiconductor Inc.
12 #include "qoriq-fman3-0.dtsi"
13 #include "qoriq-fman3-0-1g-0.dtsi"
14 #include "qoriq-fman3-0-1g-1.dtsi"
15 #include "qoriq-fman3-0-1g-2.dtsi"
16 #include "qoriq-fman3-0-1g-3.dtsi"
17 #include "qoriq-fman3-0-1g-4.dtsi"
18 #include "qoriq-fman3-0-1g-5.dtsi"
19 #include "qoriq-fman3-0-10g-0.dtsi"
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H A Dfsl-ls1043-post.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2015-2016 Freescale Semiconductor Inc.
11 #include "qoriq-fman3-0.dtsi"
12 #include "qoriq-fman3-0-1g-0.dtsi"
13 #include "qoriq-fman3-0-1g-1.dtsi"
14 #include "qoriq-fman3-0-1g-2.dtsi"
15 #include "qoriq-fman3-0-1g-3.dtsi"
16 #include "qoriq-fman3-0-1g-4.dtsi"
17 #include "qoriq-fman3-0-1g-5.dtsi"
18 #include "qoriq-fman3-0-10g-0.dtsi"
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H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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H A Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
13 Each FMan has several MACs, each implementing an Ethernet interface. Earlier
14 versions of FMan used the Datapath Three Speed Ethernet Controller (dTSEC) for
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
17 Ethernet Media Access Controller (mEMAC) to handle all speeds.
22 - fsl,fman-dtsec
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H A Dxilinx_axienet.txt1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
5 provides connectivity to an external ethernet PHY supporting different
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
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H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Controller Common Properties
10 - David S. Miller <davem@davemloft.net>
14 pattern: "^ethernet(@.*)?$"
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
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H A Dfsl,qoriq-mc-dpmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 pcs-handle:
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/freebsd/sys/contrib/device-tree/Bindings/net/pcs/
H A Dfsl,lynx-pcs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/fsl,lynx-pcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Lynx PCS
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as
14 protocol controllers. They are accessible over the Ethernet interface's MDIO
19 const: fsl,lynx-pcs
25 - compatible
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H A Dsnps,dw-xpcs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Ethernet PCS
10 - Serge Semin <fancer.lancer@gmail.com>
13 Synopsys DesignWare Ethernet Physical Coding Sublayer provides an interface
16 controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
17 optionally synthesized with a vendor-specific interface connected to
21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5ps
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dqoriq-fman3-0-10g-1-best-effort.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
41 fsl,fman-best-effort-port;
45 cell-index = <0x29>;
46 compatible = "fsl,fman-v3-port-tx";
48 fsl,fman-10g-port;
49 fsl,fman-best-effort-port;
52 ethernet@e2000 {
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H A Dqoriq-fman3-0-10g-0.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x10>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
44 cell-index = <0x30>;
45 compatible = "fsl,fman-v3-port-tx";
47 fsl,fman-10g-port;
50 ethernet@f0000 {
51 cell-index = <0x8>;
52 compatible = "fsl,fman-memac";
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H A Dqoriq-fman3-0-10g-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x11>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
44 cell-index = <0x31>;
45 compatible = "fsl,fman-v3-port-tx";
47 fsl,fman-10g-port;
50 ethernet@f2000 {
51 cell-index = <0x9>;
52 compatible = "fsl,fman-memac";
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H A Dqoriq-fman3-1-10g-0.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x10>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
44 cell-index = <0x30>;
45 compatible = "fsl,fman-v3-port-tx";
47 fsl,fman-10g-port;
50 ethernet@f0000 {
51 cell-index = <0x8>;
52 compatible = "fsl,fman-memac";
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H A Dqoriq-fman3-1-10g-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x11>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
44 cell-index = <0x31>;
45 compatible = "fsl,fman-v3-port-tx";
47 fsl,fman-10g-port;
50 ethernet@f2000 {
51 cell-index = <0x9>;
52 compatible = "fsl,fman-memac";
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H A Dqoriq-fman3-0-1g-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x29>;
44 compatible = "fsl,fman-v3-port-tx";
48 ethernet@e2000 {
49 cell-index = <1>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
53 ptp-timer = <&ptp_timer0>;
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H A Dqoriq-fman3-0-1g-2.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0xa>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x2a>;
44 compatible = "fsl,fman-v3-port-tx";
48 ethernet@e4000 {
49 cell-index = <2>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
53 ptp-timer = <&ptp_timer0>;
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H A Dqoriq-fman3-0-1g-3.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0xb>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x2b>;
44 compatible = "fsl,fman-v3-port-tx";
48 ethernet@e6000 {
49 cell-index = <3>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
53 ptp-timer = <&ptp_timer0>;
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H A Dqoriq-fman3-0-1g-5.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0xd>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x2d>;
44 compatible = "fsl,fman-v3-port-tx";
48 ethernet@ea000 {
49 cell-index = <5>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
53 ptp-timer = <&ptp_timer0>;
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H A Dqoriq-fman3-1-1g-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x29>;
44 compatible = "fsl,fman-v3-port-tx";
48 ethernet@e2000 {
49 cell-index = <1>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
53 ptp-timer = <&ptp_timer1>;
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H A Dqoriq-fman3-1-1g-2.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0xa>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x2a>;
44 compatible = "fsl,fman-v3-port-tx";
48 ethernet@e4000 {
49 cell-index = <2>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
53 ptp-timer = <&ptp_timer1>;
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