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/freebsd/share/man/man4/
H A Dmsk.430 .Nd Marvell/SysKonnect Yukon II Gigabit Ethernet adapter driver
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
50 Marvell/SysKonnect Yukon II Gigabit Ethernet controller chip.
56 features and an interrupt moderation mechanism as well as a 64-bit
71 .Bl -tag -width ".Cm 10baseT/UTP"
83 .Cm full-duplex
85 .Cm half-duplex
88 Set 100Mbps (Fast Ethernet) operation.
93 .Cm full-duplex
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H A Dmiibus.430 or have built-in transceivers that can be programmed using an MII
45 .Bl -tag -compact -width ".Xr fxp 4"
47 Attansic/Atheros L2 Fast Ethernet
49 Attansic/Atheros L1 Gigabit Ethernet
51 Atheros AR8131/AR8132 PCIe Ethernet
53 Atheros AR8121/AR8113/AR8114 PCIe Ethernet
55 ADMtek USB Ethernet
57 ASIX Electronics AX88172 USB Ethernet
59 ASIX Electronics AX88178A/AX88179 USB Ethernet
61 Broadcom NetXtreme II Gigabit Ethernet
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H A Dalc.430 .Nd Atheros AR813x/AR815x/AR816x/AR817x Gigabit/Fast Ethernet driver
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
50 and AR817x PCI Express Gigabit/Fast Ethernet controllers.
57 as well as a 64-bit multicast hash filter.
69 .Bl -tag -width ".Cm 10baseT/UTP"
78 Set 100Mbps (Fast Ethernet) operatio
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/freebsd/sys/dev/ice/
H A Dice_drv_info.h1 /* SPDX-License-Identifier: BSD-3-Clause */
65 const char ice_driver_version[] = "1.43.2-k";
72 PVID(vendor, devid, name " - 1.43.2-k")
74 PVID_OEM(vendor, devid, svid, sdevid, revid, name " - 1.43.2-k")
84 * @remark Each type of device ID needs to be listed from most-specifi
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H A Dice_devids.h1 /* SPDX-License-Identifier: BSD-3-Clause */
37 /* Intel(R) Ethernet Connection E823-L for backplane */
39 /* Intel(R) Ethernet Connection E823-L for SFP */
41 /* Intel(R) Ethernet Connection E823-
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Drealtek,rtl82xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id001c.c800
21 - ethernet-phy-id001c.c816
22 - ethernet-phy-id001c.c838
23 - ethernet-phy-id001c.c840
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H A Dmicrochip,lan95xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dnxp,tja11xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
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H A Dcortina,gemini-ethernet.txt1 Cortina Systems Gemini Ethernet Controller
4 This ethernet controller is found in the Gemini SoC family:
9 - compatible: must be "cortina,gemini-ethernet"
10 - reg: must contain the global registers and the V-bit and A-bit
12 - syscon: a phandle to the system controller
13 - #address-cells: must be specified, must be <1>
14 - #size-cells: must be specified, must be <1>
15 - ranges: should be state like this giving a 1:1 address translation
18 The subnodes represents the two ethernet ports in this device.
23 - port0: contains the resources for ethernet port 0
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H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
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H A Dcortina,gemini-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini Ethernet Controller
10 - Linus Walleij <linus.walleij@linaro.org>
13 This ethernet controller is found in the Gemini SoC family:
19 const: cortina,gemini-ethernet
23 description: must contain the global registers and the V-bit and A-bit
26 "#address-cells":
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H A Dethernet-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-widt
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H A Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
57 ethernet@e0000 {
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
62 ethernet@e2000 {
63 phy-handle = <&phy_sgmii_s7_1d>;
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H A Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
65 ethernet@e0000 {
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
70 ethernet@e2000 {
71 phy-handle = <&phy_sgmii_s3_1f>;
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H A Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
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H A Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fq
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/freebsd/sys/dev/irdma/
H A Dice_devids.h1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
4 * Copyright (c) 2019 - 2020 Intel Corporation
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
41 /* Intel(R) Ethernet Connection E823-L for backplane */
43 /* Intel(R) Ethernet Connection E823-L for SFP */
45 /* Intel(R) Ethernet Connection E823-L/X557-AT 10GBASE-T */
47 /* Intel(R) Ethernet Connection E823-L 1GbE */
49 /* Intel(R) Ethernet Connection E823-L for QSFP */
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/freebsd/contrib/ofed/libirdma/
H A Dice_devids.h1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
4 * Copyright (c) 2019 - 2020 Intel Corporation
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
41 /* Intel(R) Ethernet Connection E823-L for backplane */
43 /* Intel(R) Ethernet Connection E823-L for SFP */
45 /* Intel(R) Ethernet Connection E823-L/X557-AT 10GBASE-T */
47 /* Intel(R) Ethernet Connection E823-L 1GbE */
49 /* Intel(R) Ethernet Connection E823-L for QSFP */
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-385-clearfog-gtr-l8.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 #include "armada-385-clearfog-gtr.dtsi"
7 compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
11 sfp1: sfp-1 {
13 pinctrl-0 = <&cf_gtr_sfp1_pins>;
14 pinctrl-names = "default";
15 i2c-bus = <&i2c0>;
16 mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
17 tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
22 switch0: ethernet-switch@4 {
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
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H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dvitesse,vsc73xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
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/freebsd/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
24 compatible = "gpio-leds";
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